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X86 Debug Register
On the x86 architecture, a debug register is a register used by a processor for program debugging. There are six debug registers, named DR0...DR7, with DR4 and DR5 as obsolete synonyms for DR6 and DR7. The debug registers allow programmers to selectively enable various debug conditions associated with a set of four debug addresses. Two of these registers are used to control debug features. These registers are accessed by variants of the MOV instruction. A debug register may be either the source operand or destination operand. The debug registers are privileged resources; the MOV instructions that access them can only be executed at privilege level zero. An attempt to read or write the debug registers when executing at any other privilege level causes a general protection fault. DR0 to DR3 Each of these registers contains the linear address associated with one of four breakpoint conditions. Each breakpoint condition is further defined by bits in DR7. The debug address registers a ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
X86 Architecture
x86 (also known as 80x86 or the 8086 family) is a family of complex instruction set computer (CISC) instruction set architectures initially developed by Intel based on the Intel 8086 microprocessor and its 8088 variant. The 8086 was introduced in 1978 as a fully 16-bit extension of Intel's 8-bit 8080 microprocessor, with memory segmentation as a solution for addressing more memory than can be covered by a plain 16-bit address. The term "x86" came into being because the names of several successors to Intel's 8086 processor end in "86", including the 80186, 80286, 80386 and 80486 processors. The term is not synonymous with IBM PC compatibility, as this implies a multitude of other computer hardware. Embedded systems and general-purpose computers used x86 chips before the PC-compatible market started, some of them before the IBM PC (1981) debut. , most desktop and laptop computers sold are based on the x86 architecture family, while mobile categories such as smartphones o ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Task State Segment
The task state segment (TSS) is a structure on x86-based computers which holds information about a task. It is used by the operating system kernel for task management. Specifically, the following information is stored in the TSS: * Processor register state * I/O port permissions * Inner-level stack pointers * Previous TSS link All this information should be stored at specific locations within the TSS as specified in the IA-32 manuals. Location of the TSS The TSS may reside anywhere in memory. A segment register called the task register (TR) holds a segment selector that points to a valid TSS segment descriptor which resides in the GDT (a TSS descriptor may not reside in the LDT). Therefore, to use a TSS the following must be done by the operating system kernel: # Create a TSS descriptor entry in the GDT # Load the TR with the segment selector for that segment # Add information to the TSS in memory as needed For security purposes, the TSS should be placed in memory that is ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Operating System Technology
Operation or Operations may refer to: Arts, entertainment and media * ''Operation'' (game), a battery-operated board game that challenges dexterity * Operation (music), a term used in musical set theory * ''Operations'' (magazine), Multi-Man Publishing's house organ for articles and discussion about its wargaming products * ''The Operation'' (film), a 1973 British television film * ''The Operation'' (1990), a crime, drama, TV movie starring Joe Penny, Lisa Hartman, and Jason Beghe * ''The Operation'' (1992–1998), a reality television series from TLC * The Operation M.D., formerly The Operation, a Canadian garage rock band * "Operation", a song by Relient K from '' The Creepy EP'', 2001 Business * Business operations, the harvesting of value from assets owned by a business * Manufacturing operations, operation of a facility * Operations management, an area of management concerned with designing and controlling the process of production Military and law enforcement ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
X86 Instructions
The x86 instruction set refers to the set of instructions that x86-compatible microprocessors support. The instructions are usually part of an executable program, often stored as a computer file and executed on the processor. The x86 instruction set has been extended several times, introducing wider registers and datatypes as well as new functionality. x86 integer instructions Below is the full 8086/8088 instruction set of Intel (81 instructions total). Most if not all of these instructions are available in 32-bit mode; they just operate on 32-bit registers (eax, ebx, etc.) and values instead of their 16-bit (ax, bx, etc.) counterparts. The updated instruction set is also grouped according to architecture (i386, i486, i686) and more generally is referred to as (32-bit) x86 and (64-bit) x86-64 (also known as AMD64). Original 8086/8088 instructions Added in specific Intel processors Added with 80186/ 80188 Added with 80286 Added with 80386 Compared to e ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Test Register
A test register, in the Intel 80386 and Intel 80486 processor, was a register used by the processor, usually to do a self-test. Most of these registers were undocumented, and used by specialized software. The test registers were named TR3 to TR7. Regular programs don't usually require these registers to work. With the Pentium, the test registers were replaced by a variety of model-specific registers (MSRs). In the 80386, two test registers, TR6 and TR7, were provided for the purpose of TLB testing. TR6 was the test command register, and TR7 was the test data register. The 80486 provided three additional registers, TR3, TR4 and TR5, for testing of the L1 cache. TR3 was a data register, TR4 was an address register and TR5 was a command register. These registers were accessed by variants of the MOV instruction. A test register may either be the source operand or the destination operand. The MOV instructions are defined in both real-address mode and protected mode. The test registe ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Pentium (original)
The Pentium (also referred to as P5, its microarchitecture, or i586) is a fifth generation, 32-bit x86 microprocessor that was introduced by Intel on March 22, 1993, as the very first CPU in the Pentium brand. It was instruction set compatible with the 80486 but was a new and very different microarchitecture design from previous iterations. The P5 Pentium was the first superscalar x86 microarchitecture and the world's first superscalar microprocessor to be in mass productionmeaning it generally executes at least 2 instructions per clock mainly because of a design-first dual integer pipeline design previously thought impossible to implement on a CISC microarchitecture. Additional features include a faster floating-point unit, wider data bus, separate code and data caches, and many other techniques and features to enhance performance and support security, encryption, and multiprocessing, for workstations and servers when compared to the next best previous industry standard proce ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Control Register
A control register is a processor register which changes or controls the general behavior of a CPU or other digital device. Common tasks performed by control registers include interrupt control, switching the addressing mode, paging control, and coprocessor control. Control registers in x86 series CR0 The CR0 register is 32 bits long on the 386 and higher processors. On x64 processors in long mode, it (and the other control registers) is 64 bits long. CR0 has various control flags that modify the basic operation of the processor. Register CR0 is the 32 Bit version of the old Machine Status Word (MSW) register. The MSW register was expanded to the Control Register with the appearance of the i386 processor. CR1 Reserved, the CPU will throw a # UD exception when trying to access it. CR2 Contains a value called Page Fault Linear Address (PFLA). When a page fault occurs, the address the program attempted to access is stored in the CR2 register. CR3 Used when virtual addr ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Control Register
A control register is a processor register which changes or controls the general behavior of a CPU or other digital device. Common tasks performed by control registers include interrupt control, switching the addressing mode, paging control, and coprocessor control. Control registers in x86 series CR0 The CR0 register is 32 bits long on the 386 and higher processors. On x64 processors in long mode, it (and the other control registers) is 64 bits long. CR0 has various control flags that modify the basic operation of the processor. Register CR0 is the 32 Bit version of the old Machine Status Word (MSW) register. The MSW register was expanded to the Control Register with the appearance of the i386 processor. CR1 Reserved, the CPU will throw a # UD exception when trying to access it. CR2 Contains a value called Page Fault Linear Address (PFLA). When a page fault occurs, the address the program attempted to access is stored in the CR2 register. CR3 Used when virtual addr ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
System Management Mode
System Management Mode (SMM, sometimes called ring −2 in reference to protection rings) is an operating mode of x86 central processor units (CPUs) in which all normal execution, including the operating system, is suspended. An alternate software system which usually resides in the computer's firmware, or a hardware-assisted debugger, is then executed with high privileges. It was first released with the Intel 386SL. While initially special SL versions were required for SMM, Intel incorporated SMM in its mainline 486 and Pentium processors in 1993. AMD implemented Intel's SMM with the Am386 processors in 1991. It is available in all later microprocessors in the x86 architecture. Some ARM processors also include the Management Mode, for the system firmware (such as UEFI). Operation SMM is a special-purpose operating mode provided for handling system-wide functions like power management, system hardware control, or proprietary OEM designed code. It is intended for use onl ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
IBM 386SLC
The 386SLC was an Intel-licensed version of the 386SX (32-bit internal, 16-bit external, 24-bit memory addressing), developed and manufactured by IBM in 1991. It included power-management capabilities and an 8KB internal CPU cache, which enabled it to yield comparable performance to 386DX processors of the same clock speed, which were considerably more expensive. Known inside IBM as ''"Super Little Chip"'' for its initials, it was used in the IBM PS/2 35, 40 and 56 Series and in the IBM PS/ValuePoint 325T, but never gained much market share. This was mainly due to an agreement with Intel, in which IBM was not allowed to sell their CPUs if they were not part of a system or upgrade board. It was also marketed as an optional upgrade for 8086-equipped IBM PS/2 25 Series computers. Design and Technology Built with complementary metal oxide semiconductor (CMOS) technology, the IBM 386SLC had a 161-square millimeter die. It was available with clock speeds of 16, 20, and 25 MHz. The 2 ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
In-circuit Emulation
In-circuit emulation (ICE) is the use of a hardware device or in-circuit emulator used to debug the software of an embedded system. It operates by using a processor with the additional ability to support debugging operations, as well as to carry out the main function of the system. Particularly for older systems, with limited processors, this usually involved replacing the processor temporarily with a hardware emulator: a more powerful although more expensive version. It was historically in the form of bond-out processor which has many internal signals brought out for the purpose of debugging. These signals provide information about the state of the processor. More recently the term also covers JTAG-based hardware debuggers which provide equivalent access using on-chip debugging hardware with standard production chips. Using standard chips instead of custom bond-out versions makes the technology ubiquitous and low cost, and eliminates most differences between the development a ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Cyrix 6x86
The Cyrix 6x86 is a line of sixth-generation, 32-bit x86 microprocessors designed and released by Cyrix in 1995. Cyrix, being a fabless company, had the chips manufactured by IBM and SGS-Thomson. The 6x86 was made as a direct competitor to Intel's Pentium microprocessor line, and was pin compatible. During the 6x86's development, the majority of applications (office software as well as games) performed almost entirely integer operations. The designers foresaw that future applications would most likely maintain this instruction focus. So, to optimize the chip's performance for what they believed to be the most likely application of the CPU, the integer execution resources received most of the transistor budget. This would later prove to be a strategic mistake, as the popularity of the P5 Pentium caused many software developers to hand-optimize code in assembly language, to take advantage of the P5 Pentium's tightly pipelined and lower latency FPU. For example, the highly anticip ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
