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Tilepro64
TILE''Pro''64 is a VLIW ISA multicore processor ( Tile processor) manufactured by Tilera. It consists of a cache-coherent mesh network of 64 "tiles", where each tile houses a general purpose processor, cache, and a non-blocking router, which the tile uses to communicate with the other tiles on the processor. The short-pipeline, in-order, three-issue cores implement a VLIW instruction set. Each core has a register file and three functional units: two integer arithmetic logic units and a load-store unit. Each of the cores ("tile") has its own L1 and L2 caches plus an overall virtual L3 cache which is an aggregate of all the L2 caches. A core is able to run a full operating system on its own or multiple cores can be used to run a symmetrical multi-processing operating system. TILE''Pro''64 has four DDR2 controllers at up to 800MT/s, two 10-gigabit Ethernet XAUI interfaces, two four-lane PCIe interfaces, and a "flexible" input/output interface, which can be software-configured t ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Tilera
Tilera Corporation was a fabless semiconductor company focusing on manycore embedded processor design. The company shipped multiple processors, including the TILE64, TILE''Pro''64, and the TILE''Pro''36, TILE-Gx72, TILE-Gx36, TILE-Gx16 and TILE-Gx9. After a series of company acquisitions. Tilera's intellectual property was eventually acquired by Mellanox, which now ships products that descend from the original Tilera designs. History In 1990, Anant Agarwal led a team of researchers at Massachusetts Institute of Technology to develop scalable multi-processor system built out of large numbers of single chip processors. Alewife machines integrated both shared memory and user-level message passing for inter-node communications. In 1997, Agarwal proposed a follow-on project using a mesh technology to connect multiple cores. The follow-on project, named RAW, commenced in 1997, and was supported by DARPA/ NSF's funding of tens of millions, resulting in the first 16-processor tiles ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
PCIe
PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common motherboard interface for personal computers' graphics cards, hard disk drive host adapters, SSDs, Wi-Fi and Ethernet hardware connections. PCIe has numerous improvements over the older standards, including higher maximum system bus throughput, lower I/O pin count and smaller physical footprint, better performance scaling for bus devices, a more detailed error detection and reporting mechanism (Advanced Error Reporting, AER), and native hot-swap functionality. More recent revisions of the PCIe standard provide hardware support for I/O virtualization. The PCI Express electrical interface is measured by the number of simultaneous lanes. (A lane is a single send/receive line of data. The analogy is a highway with traffic in both directions.) ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Manycore Processors
Manycore processors are special kinds of multi-core processors designed for a high degree of parallel processing, containing numerous simpler, independent processor cores (from a few tens of cores to thousands or more). Manycore processors are used extensively in embedded computers and high-performance computing. Contrast with multicore architecture Manycore processors are distinct from multi-core processors in being optimized from the outset for a higher degree of explicit parallelism, and for higher throughput (or lower power consumption) at the expense of latency and lower single-thread performance. The broader category of multi-core processors, by contrast, are usually designed to efficiently run ''both'' parallel ''and'' serial code, and therefore place more emphasis on high single-thread performance (e.g. devoting more silicon to out of order execution, deeper pipelines, more superscalar execution units, and larger, more general caches), and shared memory. These techniq ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
6WIND
6WIND is a virtual networking software company delivering disaggregated and cloud-native solutions to CSPs and enterprises globally. The company is privately held and headquartered in the West Paris area, in Montigny-le-Bretonneux. 6WIND has a global presence with offices in the US and APAC. The company provides virtualized networking software which is deployed in bare-metal or in virtual machines on COTS servers in public & private clouds. Their solutions are disaggregated and containerized based on the cloud-native architecture. History 6WIND was founded in 2000 as a spin-out from Thales Group (previously Thomson-CSF), a provider of electronics for aerospace, defense and security. A 3.75 million euro investment from Sofinnova Partners and others was announced in 2004, and 5 million euros in 2004. Partners include Red Hat, VMware and Wind River Systems.EETimes" Wind River, 6Wind partner on multicore CPUs" January 14, 2008. Equipment vendors that provide boards and systems util ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
TILE64
TILE64 is a VLIW ISA multicore processor manufactured by Tilera. It consists of a mesh network of 64 "tiles", where each tile houses a general purpose processor, cache, and a non-blocking router, which the tile uses to communicate with the other tiles on the processor. The short-pipeline, in-order, three-issue cores implement a MIPS-inspired VLIW instruction set. Each core has a register file and three functional units: two integer arithmetic logic units and a load-store unit. Each of the cores ("tile") has its own L1 and L2 caches plus an overall virtual L3 cache which is an aggregate of all the L2 caches. A core is able to run a full operating system on its own or multiple cores can be used to run a symmetrical multi-processing operating system. TILE64 has four DDR2 controllers, two 10-gigabit Ethernet interfaces, two four-lane PCIe interfaces, and a "flexible" input/output interface, which can be software-configured to handle a number of protocols. The processor is fa ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
RGMII
The media-independent interface (MII) was originally defined as a standard interface to connect a Fast Ethernet (i.e., ) media access control (MAC) block to a PHY chip. The MII is standardized by IEEE 802.3u and connects different types of PHYs to MACs. Being ''media independent'' means that different types of PHY devices for connecting to different media (i.e. twisted pair, fiber optic, etc.) can be used without redesigning or replacing the MAC hardware. Thus any MAC may be used with any PHY, independent of the network signal transmission media. The MII can be used to connect a MAC to an external PHY using a pluggable connector, or directly to a PHY chip on the same PCB. On a PC the CNR connector Type B carries MII signals. Network data on the interface is framed using the IEEE Ethernet standard. As such it consists of a preamble, start frame delimiter, Ethernet headers, protocol-specific data and a cyclic redundancy check (CRC). The original MII transfers network data usin ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
XAUI
10 Gigabit Attachment Unit Interface (XAUI ) is a standard for extending the XGMII (10 Gigabit Media Independent Interface) between the MAC and PHY layer of 10 Gigabit Ethernet (10GbE) defined in Clause 47 of the IEEE 802.3 standard. The name is a concatenation of the Roman numeral X, meaning ten, and the initials of " Attachment Unit Interface". The purpose of the XGMII Extender, which is composed of an XGXS (XGMII Extender Sublayer) at the MAC end, an XGXS at the PHY end and a XAUI between them, is to extend the operational distance of the XGMII and to reduce the number of interface signals. Applications include extending the physical separation possible between MAC and PHY components in a 10 Gigabit Ethernet system distributed across a circuit board. Operation XGMII Extender has the following characteristics: * Simple signal mapping to the XGMII * Independent transmit and receive data paths * Four lanes conveying the XGMII 32-bit data and control * Differential signaling wit ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
PCI Express
PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common motherboard interface for personal computers' graphics cards, hard disk drive host adapters, SSDs, Wi-Fi and Ethernet hardware connections. PCIe has numerous improvements over the older standards, including higher maximum system bus throughput, lower I/O pin count and smaller physical footprint, better performance scaling for bus devices, a more detailed error detection and reporting mechanism (Advanced Error Reporting, AER), and native hot-swap functionality. More recent revisions of the PCIe standard provide hardware support for I/O virtualization. The PCI Express electrical interface is measured by the number of simultaneous lanes. (A lane is a single send/receive line of data. The analogy is a highway with traffic in both directions.) ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Memory Controller
The memory controller is a digital circuit that manages the flow of data going to and from the computer's main memory. A memory controller can be a separate chip or integrated into another chip, such as being placed on the same die or as an integral part of a microprocessor; in the latter case, it is usually called an integrated memory controller (IMC). A memory controller is sometimes also called a memory chip controller (MCC) or a memory controller unit (MCU). A common form of memory controller is the memory management unit (MMU) which in many operating systems implements virtual addressing. History Most modern desktop or workstation microprocessors use an ''integrated memory controller'' (IMC), including microprocessors from Intel, AMD, and those built around the ARM architecture. Prior to K8 (circa 2003), AMD microprocessors had a memory controller implemented on their motherboard's northbridge. In K8 and later, AMD employed an integrated memory controller. Likew ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
90 Nanometer
The 90 nm process refers to the level of MOSFET (CMOS) fabrication process technology that was commercialized by the 2003–2005 timeframe, by leading semiconductor companies like Toshiba, Sony, Samsung, IBM, Intel, Fujitsu, TSMC, Elpida, AMD, Infineon, Texas Instruments and Micron Technology. The origin of the 90 nm value is historical, it reflects a trend of 70% scaling every 2–3 years. The naming is formally determined by the International Technology Roadmap for Semiconductors (ITRS). The 193 nm wavelength was introduced by many (but not all) companies for lithography of critical layers mainly during the 90 nm node. Yield issues associated with this transition (due to the use of new photoresists) were reflected in the high costs associated with this transition. Even more significantly, the 300 mm wafer size became mainstream at the 90 nm node. The previous wafer size was 200 mm diameter. History A 90nm silicon MOSFET was fabri ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Cache Coherence
In computer architecture, cache coherence is the uniformity of shared resource data that ends up stored in multiple local caches. When clients in a system maintain caches of a common memory resource, problems may arise with incoherent data, which is particularly the case with CPUs in a multiprocessing system. In the illustration on the right, consider both the clients have a cached copy of a particular memory block from a previous read. Suppose the client on the bottom updates/changes that memory block, the client on the top could be left with an invalid cache of memory without any notification of the change. Cache coherence is intended to manage such conflicts by maintaining a coherent view of the data values in multiple caches. Overview In a shared memory multiprocessor system with a separate cache memory for each processor, it is possible to have many copies of shared data: one copy in the main memory and one in the local cache of each processor that requested it. When on ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Kilobyte
The kilobyte is a multiple of the unit byte for digital information. The International System of Units (SI) defines the prefix ''kilo'' as 1000 (103); per this definition, one kilobyte is 1000 bytes.International Standard IEC 80000-13 Quantities and Units – Part 13: Information science and technology, International Electrotechnical Commission (2008). The internationally recommended unit symbol for the kilobyte is kB. In some areas of information technology, particularly in reference to solid-state memory capacity, ''kilobyte'' instead typically refers to 1024 (210) bytes. This arises from the prevalence of sizes that are powers of two in modern digital memory architectures, coupled with the accident that 210 differs from 103 by less than 2.5%. A kibibyte is defined by Clause 4 of IEC 80000-13 as 1024 bytes. Definitions and usage Base 10 (1000 bytes) In the International System of Units (SI) the prefix ''kilo'' means 1000 (103); therefore, one kilobyte is 1000 bytes. The uni ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
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