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TAPAs Model Checker
TAPAs is a tool for specifying and analyzing concurrent systems. Its aim is to support teaching of process algebras. Systems are described as process algebra terms that are then mapped to labeled transition systems (LTSs). Properties can be verified by checking equivalences between concrete and abstract system descriptions or by model checking temporal formulas (expressed as μ-calculus or ACTL) over the obtained LTS. A key feature of TAPAs that makes it particularly suited for teaching is that it maintains a consistent graphical and textual representation of each system. After a change in the graphic notation, the textual representation is updated immediately; but after textual modifications, the update of the graphical representation has to be manually triggered. In TAPAs, concurrent systems are described by means of processes, which are nondeterministic descriptions of system behaviors, and process systems, which are obtained by process compositions. Notably, processes can b ...
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Labelled Transition System
In theoretical computer science, a transition system is a concept used in the study of computation. It is used to describe the potential behavior of discrete systems. It consists of states and transitions between states, which may be labeled with labels chosen from a set; the same label may appear on more than one transition. If the label set is a singleton, the system is essentially unlabeled, and a simpler definition that omits the labels is possible. Transition systems coincide mathematically with abstract rewriting systems (as explained further in this article) and directed graphs. They differ from finite-state automata in several ways: * The set of states is not necessarily finite, or even countable. * The set of transitions is not necessarily finite, or even countable. * No "start" state or "final" states are given. Transition systems can be represented as directed graphs. Formal definition Formally, a transition system is a pair (S, \rightarrow) where S is a set of s ...
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CTMC
A continuous-time Markov chain (CTMC) is a continuous stochastic process in which, for each state, the process will change state according to an exponential random variable and then move to a different state as specified by the probabilities of a stochastic matrix. An equivalent formulation describes the process as changing state according to the least value of a set of exponential random variables, one for each possible state it can move to, with the parameters determined by the current state. An example of a CTMC with three states \ is as follows: the process makes a transition after the amount of time specified by the holding time—an exponential random variable E_i, where ''i'' is its current state. Each random variable is independent and such that E_0\sim \text(6), E_1\sim \text(12) and E_2\sim \text(18). When a transition is to be made, the process moves according to the jump chain, a discrete-time Markov chain with stochastic matrix: :\begin 0 & \frac & \frac \\ \frac & ...
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LNCS
''Lecture Notes in Computer Science'' is a series of computer science books published by Springer Science+Business Media since 1973. Overview The series contains proceedings, post-proceedings, monographs, and Festschrifts. In addition, tutorials, state-of-the-art surveys, and "hot topics" are increasingly being included. The series is indexed by DBLP. See also *''Monographiae Biologicae'', another monograph series published by Springer Science+Business Media *''Lecture Notes in Physics'' *''Lecture Notes in Mathematics'' *''Electronic Workshops in Computing'', published by the British Computer Society Sir Maurice Wilkes served as the first President of BCS in 1957 BCS, The Chartered Institute for IT, known as the British Computer Society until 2009, is a professional body and a learned society that represents those working in infor ... References External links * Publications established in 1973 Computer science books Series of non-fiction books Springer ...
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List Of Model Checking Tools
This article lists model checking tools and gives an overview of the functionality of each. Overview of some model checking tools The following table includes model checkers that have # a web site from which it can be downloaded, # a declared license, # a description published in archived literature, and # a Wikipedia article describing it. In the below table, the following abbreviations are used: * Equivalences: **SB: Strong Bisimulation **WB: Weak Bisimulation **BB: Branching Bisimulation **STE: Strong Trace Equivalence **WTE: Weak Trace Equivalence **me: May Equivalence **ME: Must Equivalence **OE: Observational Equivalence **SE: Safety Equivalence **t*E: tau*.a Equivalence *Software license: ** FUSC: Free Under Specific Condition (e.g., free for academics) Modelling languages *CCSP: A process calculus obtained from CCS by incorporating some operators of CSP. It is defined by Olderog E.R. Olderog''Operational Petri net semantics for CCSP''/ref> and by van Glabbeek/Vaandr ...
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University Of Florence
The University of Florence (Italian: ''Università degli Studi di Firenze'', UniFI) is an Italian public research university located in Florence, Italy. It comprises 12 schools and has around 50,000 students enrolled. History The first university in Florence was the Studium Generale, which was established by the Florentine Republic in 1321. The Studium was recognized by Pope Clement VI in 1349, and authorized to grant regular degrees. The Pope also established that the first Italian faculty of theology would be in Florence. The Studium became an imperial university in 1364, but was moved to Pisa in 1473 when Lorenzo the Magnificent gained control of Florence. Charles VIII moved it back from 1497 to 1515, but it was moved to Pisa again when the Medici family returned to power. The modern university dates from 1859, when a group of disparate higher-studies institutions grouped together in the Istituto di Studi Pratici e di Perfezionamento, which a year later was recognized as ...
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Consiglio Nazionale Delle Ricerche
The National Research Council (Italian: ''Consiglio Nazionale delle Ricerche, CNR'') is the largest research council in Italy. As a public organisation, its remit is to support scientific and technological research. Its headquarters are in Rome. History The institution was founded in 1923. The first president was Vito Volterra, succeeded by Guglielmo Marconi. The process of improvement of the national scientific research, through the use of specific laws, (see Law 59/1997), affects many research organisations, and amongst them is CNR, whose "primary function is to carry on, through its own organs, advanced basic and applied research, both to develop and maintain its own scientific competitiveness, and to be ready to take part effectively in a timely manner in the strategic fields defined by the national planning system". On 23 December 1987, CNR registered the first Italian internet domain: cnr.it Reorganisation With the issuing of the legislative decree of 30 January 1999, n. ...
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ISTI
The "Alessandro Faedo" Istituto di Scienza e Tecnologie dell'Informazione (''Institute of Information Science and Technologies'') is an institute of the Italian National Research Council (CNR). The institute is located in the CNR research area in the Ghezzano Province of Pisa about 5 km from San Giuliano Terme. The institute was founded in 2002 as a merge of two previous CNR institutes: Istituto CNUCE and Istituto di Elaborazione dell’Informazione (IEI). The institute is named in honor of Alessandro Faedo, former President of CNR and former rector of the University of Pisa, for his important contributions to the development of Computer Science in Italy. The mission of the institute is ''producing scientific excellence and playing an active role in technology transfer'' in the field of Computer Science. In 2022 the research staff of the institute counts more than 120 researchers and a total staff (including PhD students and fellows) of around 230. Since 1 April 2019 the ISTI ...
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Pisa
Pisa ( , or ) is a city and ''comune'' in Tuscany, central Italy, straddling the Arno just before it empties into the Ligurian Sea. It is the capital city of the Province of Pisa. Although Pisa is known worldwide for its leaning tower, the city contains more than twenty other historic churches, several medieval palaces, and bridges across the Arno. Much of the city's architecture was financed from its history as one of the Italian maritime republics. The city is also home to the University of Pisa, which has a history going back to the 12th century, the Scuola Normale Superiore di Pisa, founded by Napoleon in 1810, and its offshoot, the Sant'Anna School of Advanced Studies.Scuola Superiore Sant'Anna di Pisa
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Model Checker
In computer science, model checking or property checking is a method for checking whether a finite-state model of a system meets a given specification (also known as correctness). This is typically associated with hardware or software systems, where the specification contains liveness requirements (such as avoidance of livelock) as well as safety requirements (such as avoidance of states representing a system crash). In order to solve such a problem algorithmically, both the model of the system and its specification are formulated in some precise mathematical language. To this end, the problem is formulated as a task in logic, namely to check whether a structure satisfies a given logical formula. This general concept applies to many kinds of logic and many kinds of structures. A simple model-checking problem consists of verifying whether a formula in the propositional logic is satisfied by a given structure. Overview Property checking is used for verification when two de ...
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Temporal Logic
In logic, temporal logic is any system of rules and symbolism for representing, and reasoning about, propositions qualified in terms of time (for example, "I am ''always'' hungry", "I will ''eventually'' be hungry", or "I will be hungry ''until'' I eat something"). It is sometimes also used to refer to tense logic, a modal logic-based system of temporal logic introduced by Arthur Prior in the late 1950s, with important contributions by Hans Kamp. It has been further developed by computer scientists, notably Amir Pnueli, and logicians. Temporal logic has found an important application in formal verification, where it is used to state requirements of hardware or software systems. For instance, one may wish to say that ''whenever'' a request is made, access to a resource is ''eventually'' granted, but it is ''never'' granted to two requestors simultaneously. Such a statement can conveniently be expressed in a temporal logic. Motivation Consider the statement "I am hungry". Though its ...
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Bisimulation
In theoretical computer science a bisimulation is a binary relation between state transition systems, associating systems that behave in the same way in that one system simulates the other and vice versa. Intuitively two systems are bisimilar if they, assuming we view them as playing a ''game'' according to some rules, match each other's moves. In this sense, each of the systems cannot be distinguished from the other by an observer. Formal definition Given a labelled state transition system (S, \Lambda, →), where S is a set of states, \Lambda is a set of labels and → is a set of labelled transitions (i.e., a subset of S \times \Lambda \times S), a bisimulation is a binary relation R \subseteq S \times S, such that both R and its converse R^T are simulations. From this follows that the symmetric closure of a bisimulation is a bisimulation, and that each symmetric simulation is a bisimulation. Thus some authors define bisimulation as a symmetric simulation. Equivalentl ...
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Formal Equivalence Checking
Formal equivalence checking process is a part of electronic design automation (EDA), commonly used during the development of digital integrated circuits, to formally prove that two representations of a circuit design exhibit exactly the same behavior. Equivalence checking and levels of abstraction In general, there is a wide range of possible definitions of functional equivalence covering comparisons between different levels of abstraction and varying granularity of timing details. *The most common approach is to consider the problem of machine equivalence which defines two synchronous design specifications functionally equivalent if, clock by clock, they produce ''exactly'' the same sequence of output signals for ''any'' valid sequence of input signals. *Microprocessor designers use equivalence checking to compare the functions specified for the instruction set architecture (ISA) with a register transfer level (RTL) implementation, ensuring that any program executed on both ...
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