|
Ryzen
Ryzen ( ) is a brand of multi-core x86-64 microprocessors designed and marketed by AMD for desktop, mobile, server, and embedded platforms based on the Zen microarchitecture. It consists of central processing units (CPUs) marketed for mainstream, enthusiast, server, and workstation segments and accelerated processing units (APUs) marketed for mainstream and entry-level segments and embedded systems applications. AMD announced a new series of processors on December 13, 2016, named "Ryzen", and delivered them in Q1 2017, the first of several generations. The 1000 series featured up to eight cores and 16 threads, with a 52% instructions per cycle (IPC) increase over their prior CPU products. The second generation of Ryzen processors, the Ryzen 2000 series, released in April 2018, featured the Zen+ microarchitecture, a 12 nm process (GlobalFoundries); the aggregate performance increased 10% (of which approximately 3% was IPC, 6% was frequency); most importantly, Zen+ fixed ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Secure Memory Encryption
Zen is the codename for the first iteration in a family of computer processor microarchitectures of the same name from AMD. It was first used with their Ryzen series of CPUs in February 2017. The first Zen-based preview system was demonstrated at E3 2016, and first substantially detailed at an event hosted a block away from the Intel Developer Forum 2016. The first Zen-based CPUs, codenamed "Summit Ridge", reached the market in early March 2017, Zen-derived Epyc server processors launched in June 2017 and Zen-based APUs arrived in November 2017. Zen is a clean sheet design that differs from AMD's previous long-standing Bulldozer architecture. Zen-based processors use a 14 nm FinFET process, are reportedly more energy efficient, and can execute significantly more instructions per cycle. SMT has been introduced, allowing each core to run two threads. The cache system has also been redesigned, making the L1 cache write-back. Zen processors use three different sockets: desktop and ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Socket AM4
Socket AM4 is a PGA microprocessor socket used by AMD's central processing units (CPUs) built on the Zen (including Zen+, Zen 2 and Zen 3) and Excavator microarchitectures. ''AM4'' was launched in September 2016 and was designed to replace the sockets AM3+, FM2+ and FS1b as a single platform. It has 1331 pin slots and is the first from AMD to support DDR4 memory as well as achieve unified compatibility between high-end CPUs (previously using Socket AM3+) and AMD's lower-end APUs (on various other sockets). In 2017, AMD made a commitment to using the AM4 platform with socket 1331 until 2020. Features * Support for Zen (including Zen+, Zen 2 and Zen 3) based family of CPUs and APUs (Ryzen, Athlon), as well as for some A-Series APUs and Athlon X4 CPUs (Bristol Ridge based on the Excavator microarchitecture) * Supports PCIe 3.0 and PCIe 4.0 * Supports up to 4 modules of DDR4 RAM in dual-channel configuration Heatsink The AM4 socket specifies the 4 holes for fastening the ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Socket AM5
Socket AM5 (LGA 1718) is a zero insertion force flip-chip land grid array (LGA) CPU socket designed by Advanced Micro Devices, that is used for AMD Ryzen microprocessors starting with the Zen 4 microarchitecture. AM5 replaces the Socket AM4 and is AMD's first LGA socket designed for mainstream, non-enthusiast CPUs. AMD officially confirmed details about the Ryzen 7000 series platform, including support for PCI Express 5.0 and DDR5 SDRAM, DDR5 as part of their 2022 Product Premiere. Background In March 2017, with the launch of its new Zen processors, AMD used the AM4 socket that they had previously used with their Bristol Ridge (derived from Excavator) powered Athon-X4 and some A-Series, a pin grid array (PGA) socket that they promised to support until 2020. In April 2022, AMD released its final CPU for the AM4 socket, the 5800X3D, which featured 96MB of 3D-stacked L3 cache. Announcement At Consumer Electronics Show#2022, CES 2022, AMD CEO Lisa Su unveiled the AM5 socket and t ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Socket STRX4
Socket sTRX4, also known as Socket SP3r3, is a land grid array (LGA) CPU socket designed by AMD supporting its Zen 2-based Castle Peak Ryzen Threadripper desktop processors, launched on November 25, 2019 for the high-end desktop and workstation platforms Socket sTRX4 is the direct successor to Socket TR4 used in the first- and second-generation Ryzen Threadripper products. It is physically identical to, but electrically incompatible with, both TR4 and AMD's server Socket SP3. While Socket SP3 doesn't require a chipset, instead utilizing a system-on-a-chip design, Socket sTRX4 and its predecessor require a chipset to provide improved connectivity and functionality. For Socket sTRX4, the TRX40 chipset was developed, which provides a total of 88 PCIe 4.0 lanes, an increase from the 66 PCIe 3.0 lanes on its predecessor platform. Also it no longer features a built-in High Definition Audio interface; instead motherboard manufacturers are including a separate audio controller onbo ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
FMA3 Instruction Set
The FMA instruction set is an extension to the 128 and 256-bit Streaming SIMD Extensions instructions in the x86 microprocessor instruction set to perform fused multiply–add (FMA) operations."FMA3 and FMA4 are not instruction sets, they are individual instructions -- fused multiply add. They could be quite useful depending on how Intel and AMD implement them" There are two variants: * FMA4 is supported in AMD processors starting with the Bulldozer architecture. FMA4 was performed in hardware before FMA3 was. Support for FMA4 has been removed since Zen 1. * FMA3 is supported in AMD processors starting with the Piledriver architecture and Intel starting with Haswell processors and Broadwell processors since 2014. Instructions FMA3 and FMA4 instructions have almost identical functionality, but are not compatible. Both contain fused multiply–add (FMA) instructions for floating-point scalar and SIMD operations, but FMA3 instructions have three operands, while FMA4 ones have ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Socket TR4
Socket TR4, also known as ''Socket SP3r2'', is a zero insertion force land grid array (LGA) CPU socket designed by AMD supporting its first- and second-generation Zen-based Ryzen Threadripper desktop processors, launched on August 10, 2017 for the high-end desktop and workstation platforms. It was succeeded by Socket sTRX4 for the third generation of Ryzen Threadripper processors. Socket TR4 is AMD's second LGA socket for a consumer product after the short lived Socket 1207 FX. It is physically identical to, but electrically incompatible with both AMD's server Socket SP3, and Socket TR4's successor socket, Socket sTRX4. While Socket SP3 does not require a chipset, instead utilising a system-on-a-chip design, Socket TR4 and its successor require a chipset to provide improved functionality. For Socket TR4, the AMD X399 chipset was developed, which supports a total of 64 PCIe 4.0 lanes for quad SLI/CrossFire configurations. The socket is made by both Foxconn and Lotes. Se ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
AMD FX
AMD FX was a series of high-end AMD microprocessors for personal computers which debuted in 2011, claimed as AMD's first native 8-core desktop processor. The line was introduced with the Bulldozer microarchitecture at launch (codename Zambezi), and was then succeeded by its derivative Piledriver in 2012 (codename Vishera). The line aimed at competing with the Intel Core line of desktop processors, and in particular the Sandy Bridge and Ivy Bridge architectures. AMD's successor architecture, Zen, was released in 2017 under the Ryzen brand, replacing the FX series and competing with Intel's Skylake architecture. History Prior to FX Launch In the years prior to the AMD FX range of processors, the AMD Phenom II and Athlon II lineup of processors, while not beating Intel's Core lineup in raw performance, were generally competitive when their price was taken into account. By the end of Phenom's lifespan, however, Intel's Sandy Bridge architecture could provide performance th ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
AVX-512
AVX-512 are 512-bit extensions to the 256-bit Advanced Vector Extensions SIMD instructions for x86 instruction set architecture (ISA) proposed by Intel in July 2013, and implemented in Intel's Xeon Phi x200 (Knights Landing) and Skylake-X CPUs; this includes the Core-X series (excluding the Core i5-7640X and Core i7-7740X), as well as the new Xeon Scalable Processor Family and Xeon D-2100 Embedded Series. AVX-512 consists of multiple extensions that may be implemented independently. This policy is a departure from the historical requirement of implementing the entire instruction block. Only the core extension AVX-512F (AVX-512 Foundation) is required by all AVX-512 implementations. Besides widening most 256-bit instructions, the extensions introduce various new operations, such as new data conversions, scatter operations, and permutations. The number of AVX registers is increased from 16 to 32, and eight new "mask registers" are added, which allow for variable selection and blendi ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Bit Manipulation Instruction Sets
Bit manipulation instructions sets (BMI sets) are extensions to the x86 instruction set architecture for microprocessors from Intel and AMD. The purpose of these instruction sets is to improve the speed of bit manipulation. All the instructions in these sets are non-SIMD and operate only on general-purpose registers. There are two sets published by Intel: BMI (now referred to as BMI1) and BMI2; they were both introduced with the Haswell microarchitecture with BMI1 matching features offered by AMD's ABM instruction set and BMI2 extending them. Another two sets were published by AMD: ABM (''Advanced Bit Manipulation'', which is also a subset of SSE4a implemented by Intel as part of SSE4.2 and BMI1), and TBM (''Trailing Bit Manipulation'', an extension introduced with Piledriver-based processors as an extension to BMI1, but dropped again in Zen-based processors). ABM (Advanced Bit Manipulation) AMD was the first to introduce the instructions that now form Intel's BMI1 as part o ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
GlobalFoundries
GlobalFoundries Inc. (GF or GloFo) is a multinational semiconductor contract manufacturing and design company incorporated in the Cayman Islands and headquartered in Malta, New York. Created by the divestiture of the manufacturing arm of AMD, the company was privately owned by Mubadala Investment Company, the sovereign wealth fund of the United Arab Emirates, until an initial public offering (IPO) in October 2021. The company manufactures chips designed for markets such as mobility, automotive, computing and wired connectivity, consumer internet of things (IoT) and industrial. As of 2021, GlobalFoundries is the fourth-largest semiconductor manufacturer; it produces chips for more than 7% of the $86 billion semiconductor manufacturing services industry. It is the only one with operations in Singapore, the European Union, and the United States: one 200 mm and one 300 mm wafer fabrication plant in Singapore; one 300 mm plant in Dresden, Germany; one 200 mm plan ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
X86-64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging mode. With 64-bit mode and the new paging mode, it supports vastly larger amounts of virtual memory and physical memory than was possible on its 32-bit predecessors, allowing programs to store larger amounts of data in memory. x86-64 also expands general-purpose registers to 64-bit, and expands the number of them from 8 (some of which had limited or fixed functionality, e.g. for stack management) to 16 (fully general), and provides numerous other enhancements. Floating-point arithmetic is supported via mandatory SSE2-like instructions, and x87/ MMX style registers are generally not used (but still available even in 64-bit mode); instead, a set of 16 vector registers, 128 bits each, is used. (Each register can store one or two double-preci ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
RDRAND
RDRAND (for "read random"; known as Intel Secure Key Technology, previously known as Bull Mountain) is an instruction for returning random numbers from an Intel on-chip hardware random number generator which has been seeded by an on-chip entropy source. Intel introduced the feature around 2012, and AMD added support for the instruction in June 2015. (RDRAND is available in Ivy Bridge processors and is part of the Intel 64 and IA-32 instruction set architectures.) The random number generator is compliant with security and cryptographic standards such as NIST SP 800-90A, FIPS 140-2, and ANSI X9.82. Intel also requested Cryptography Research Inc. to review the random number generator in 2012, which resulted in the paper ''Analysis of Intel's Ivy Bridge Digital Random Number Generator''. RDSEED is similar to RDRAND and provides lower-level access to the entropy-generating hardware. The RDSEED generator and processor instruction rdseed are available with Intel Broadwell CPUs and A ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
