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Radeon HD 2000 Series
The graphics processing unit (GPU) codenamed Radeon R600 is the foundation of the Radeon HD 2000 series and the FireGL 2007 series video cards developed by ATI Technologies. The HD 2000 cards competed with nVidia's GeForce 8 series. Architecture This article is about all products under the brand "Radeon HD 2000 Series". They all contain a GPU which implements TeraScale 1, ATI's first Unified shader model microarchitecture for PCs. Video acceleration The Unified Video Decoder (UVD) SIP core is on-die in the HD 2400 and the HD 2600. The HD 2900 GPU dies do not have a UVD core, as its stream processors were powerful enough to handle most of the steps of video acceleration in its stead except for entropy decoding and bitstream processing which are left for the CPU to perform. Other features HDTV encoding support is implemented via the integrated AMD Xilleon encoder; the companion ''Rage Theater'' chip used on the Radeon X1000 series was replaced with the digital ''Theater 200' ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
TeraScale (microarchitecture)
TeraScale is the codename for a family of graphics processing unit microarchitectures developed by ATI Technologies/Advanced Micro Devices, AMD and their second microarchitecture implementing the unified shader model following ''Xenos (graphics chip), Xenos''. TeraScale replaced the old Pipeline (computing), fixed-pipeline microarchitectures and competed directly with Nvidia's first unified shader microarchitecture named Tesla (microarchitecture), Tesla. TeraScale was used in Radeon HD 2000 series, HD 2000 manufactured in 80 nm and 65 nm process, 65 nm, Radeon HD 3000 series, HD 3000 manufactured in 65 nm and 55 nm, Radeon HD 4000 series, HD 4000 manufactured in 55 nm and 40 nm, Radeon HD 5000 series, HD 5000 and Radeon HD 6000 series, HD 6000 manufactured in 40 nm. TeraScale was also used in the AMD Accelerated Processing Units code-named "Brazos", "Llano", "Trinity" and "Richland". TeraScale is even found in some of the succeeding graphics card ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Semiconductor Intellectual Property Core
In electronic design, a semiconductor intellectual property core (SIP core), IP core, or IP block is a reusable unit of logic, cell, or integrated circuit layout design that is the intellectual property of one party. IP cores can be licensed to another party or owned and used by a single party. The term comes from the licensing of the patent or source code copyright that exists in the design. Designers of application-specific integrated circuits (ASIC) and systems of field-programmable gate array (FPGA) logic can use IP cores as building blocks. History The licensing and use of IP cores in chip design came into common practice in the 1990s. There were many licensors and also many foundries competing on the market. In 2013, the most widely licensed IP cores are from Arm Holdings (43.2% market share), Synopsys Inc. (13.9% market share), Imagination Technologies (9% market share) and Cadence Design Systems (5.1% market share). Types of IP cores The use of an IP core in chip ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Sapphire ATI Radeon HD 2400 XT
Sapphire is a precious gemstone, a variety of the mineral corundum, consisting of aluminium oxide () with trace amounts of elements such as iron, titanium, chromium, vanadium, or magnesium. The name sapphire is derived via the Latin "sapphirus" from the Greek "sappheiros", which referred to lapis lazuli. It is typically blue, but natural "fancy" sapphires also occur in yellow, purple, orange, and green colors; "parti sapphires" show two or more colors. Red corundum stones also occur, but are called rubies rather than sapphires. Pink-colored corundum may be classified either as ruby or sapphire depending on locale. Commonly, natural sapphires are cut and polished into gemstones and worn in jewelry. They also may be created synthetically in laboratories for industrial or decorative purposes in large crystal boules. Because of the remarkable hardness of sapphires 9 on the Mohs scale (the third hardest mineral, after diamond at 10 and moissanite at 9.5) sapphires are also used i ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
GDDR4
GDDR4 SDRAM, an abbreviation for Graphics Double Data Rate 4 Synchronous Dynamic Random-Access Memory, is a type of graphics card memory (SGRAM) specified by the JEDEC Semiconductor Memory Standard. It is a rival medium to Rambus's XDR DRAM. GDDR4 is based on DDR3 SDRAM technology and was intended to replace the DDR2-based GDDR3, but it ended up being replaced by GDDR5 within a year. History * On October 26, 2005, Samsung announced that it developed the first GDDR4 memory, a 256-Mbit chip running at 2.5 Gbit/s. Samsung also revealed plans to sample and mass-produce GDDR4 SDRAM rated at 2.8 Gbit/s per pin. * In 2005, Hynix developed the first 512-Mbit GDDR4 memory chip. * On February 14, 2006, Samsung announced the development of 32-bit 512-Mbit GDDR4 SDRAM capable of transferring 3.2 Gbit/s per pin, or 12.8 GB/s for the module. * On July 5, 2006, Samsung announced the mass-production of 32-bit 512-Mbit GDDR4 SDRAM rated at 2.4 Gbit/s per pin, or 9.6 ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
GDDR3
GDDR3 SDRAM (Graphics Double Data Rate 3 SDRAM) is a type of DDR SDRAM specialized for graphics processing units (GPUs) offering less access latency and greater device bandwidths. Its specification was developed by ATI Technologies in collaboration with DRAM vendors including Elpida Memory, Hynix Semiconductor, Infineon (later Qimonda) and Micron. It was later adopted as a JEDEC standard. Overview It has much the same technological base as DDR2, but the power and heat dispersal requirements have been reduced somewhat, allowing for higher performance memory modules, and simplified cooling systems. GDDR3 is not related to the JEDEC DDR3 specification. This memory uses internal terminators, enabling it to better handle certain graphics demands. To improve throughput, GDDR3 memory transfers 4 bits of data per pin in 2 clock cycles. The GDDR3 interface transfers two 32 bit wide data words per clock cycle from the I/O pins. Corresponding to the 4n-prefetch a single write or re ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
ATI CrossFire
AMD CrossFire (also known as CrossFireX) is a brand name for the multi-GPU technology by Advanced Micro Devices, originally developed by ATI Technologies. The technology allows up to four GPUs to be used in a single computer to improve graphics performance. Associated technology used in mobile computers with external graphics cards, such as in laptops or notebooks, is called AMD Hybrid Graphics. The CrossFire brand name was retired by AMD in September 2017, however the company continues to develop and support the technology for DirectX 11 applications. For DirectX 12 applications, AMD has the mGPU (also known as multi-GPU) branding, with the difference being that software developers must create mGPU compatible profiles for their applications where before AMD created the profiles for DirectX 11 applications. Configurations First-generation CrossFire was first made available to the public on September 27, 2005. The system required a CrossFire-compliant motherboard with a pair of ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Dolby AC-3
Dolby Digital, originally synonymous with Dolby AC-3, is the name for what has now become a family of audio compression technologies developed by Dolby Laboratories. Formerly named Dolby Stereo Digital until 1995, the audio compression is lossy (except for Dolby TrueHD), based on the modified discrete cosine transform (MDCT) algorithm. The first use of Dolby Digital was to provide digital sound in cinemas from 35 mm film prints; today, it is also used for applications such as TV broadcast, radio broadcast via satellite, digital video streaming, DVDs, Blu-ray discs and game consoles. The main basis of the Dolby AC-3 multi-channel audio coding standard is the modified discrete cosine transform (MDCT), a lossy audio compression algorithm. It is a modification of the discrete cosine transform (DCT) algorithm, which was first proposed by Nasir Ahmed in 1972 and was originally intended for image compression. The DCT was adapted into the modified discrete cosine transform (MDCT) ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
LPCM
Pulse-code modulation (PCM) is a method used to digitally represent sampled analog signals. It is the standard form of digital audio in computers, compact discs, digital telephony and other digital audio applications. In a PCM stream, the amplitude of the analog signal is sampled regularly at uniform intervals, and each sample is quantized to the nearest value within a range of digital steps. Linear pulse-code modulation (LPCM) is a specific type of PCM in which the quantization levels are linearly uniform. This is in contrast to PCM encodings in which quantization levels vary as a function of amplitude (as with the A-law algorithm or the μ-law algorithm). Though ''PCM'' is a more general term, it is often used to describe data encoded as LPCM. A PCM stream has two basic properties that determine the stream's fidelity to the original analog signal: the sampling rate, which is the number of times per second that samples are taken; and the bit depth, which determines the num ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
High-Definition Multimedia Interface
High-Definition Multimedia Interface (HDMI) is a proprietary audio/video interface for transmitting uncompressed video data and compressed or uncompressed digital audio data from an HDMI-compliant source device, such as a display controller, to a compatible computer monitor, video projector, digital television, or digital audio device. HDMI is a digital replacement for analog video standards. HDMI implements the EIA/CEA-861 standards, which define video formats and waveforms, transport of compressed and uncompressed LPCM audio, auxiliary data, and implementations of the VESA EDID. CEA-861 signals carried by HDMI are electrically compatible with the CEA-861 signals used by the Digital Visual Interface (DVI). No signal conversion is necessary, nor is there a loss of video quality when a DVI-to-HDMI adapter is used. The Consumer Electronics Control (CEC) capability allows HDMI devices to control each other when necessary and allows the user to operate multiple devices with on ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
High-bandwidth Digital Content Protection
High-bandwidth Digital Content Protection (HDCP) is a form of digital copy protection developed by Intel Corporation to prevent copying of digital audio and video content as it travels across connections. Types of connections include DisplayPort (DP), Digital Visual Interface (DVI), and High-Definition Multimedia Interface (HDMI), as well as less popular or now deprecated protocols like Gigabit Video Interface (GVIF) and Unified Display Interface (UDI). The system is meant to stop HDCP-encrypted content from being played on unauthorized devices or devices which have been modified to copy HDCP content. Before sending data, a transmitting device checks that the receiver is authorized to receive it. If so, the transmitter encrypts the data to prevent eavesdropping as it flows to the receiver. In order to make a device that plays HDCP-enabled content, the manufacturer must obtain a license for the patent from Intel subsidiary Digital Content Protection LLC, pay an annual fee, and sub ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
TMDS
Transition-minimized differential signaling (TMDS), a technology for transmitting high-speed serial data, is used by the DVI and HDMI video interfaces, as well as by other digital communication interfaces. The transmitter incorporates an advanced coding algorithm which reduces electromagnetic interference over copper cables and enables robust clock recovery at the receiver to achieve high skew tolerance for driving longer cables as well as shorter low-cost cables. Coding The method is a form of 8b/10b encoding but using a code-set that differs from the original IBM form. A two-stage process converts an input of 8 bits into a 10 bit code with particular desirable properties. In the first stage, the first bit is untransformed and each subsequent bit is either XOR or XNOR transformed against the previous bit. The encoder chooses between XOR and XNOR by determining which will result in the fewest transitions; the ninth bit encodes which operation was used. In the second stage, the ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
