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List Of Russian Microprocessors
This is the list of Russian microprocessors, sorted by manufacturer ;MCST * Elbrus 2000 – implements VLIW architecture, 300 MHz clock rate, developed by MCST * Elbrus-S * Elbrus-1S+ – single-core evolution of Elbrus 2000 SoC, 1000 MHz clock rate + GPU * Elbrus-2S+ – dual-core evolution of Elbrus 2000, 500 MHz clock rate + four DSP cores (ELcore-09) * Elbrus-2SM – dual-core evolution of Elbrus 2000, 300 MHz clock rate * Elbrus-4S – quad-core evolution of Elbrus 2000, 800 MHz clock rate * Elbrus-8S – octa-core evolution of Elbrus 2000, 1.3 GHz clock rate * MCST-R150 * MCST-R500 * MCST-R500S – SPARC V8 dual-core 500 MHz * MCST-R1000 – SPARC V9 quad-core 1 GHz * MCST-4R – 64-bit, 4-core, 2w in-order superscalar, implements SPARC V9 instruction set architecture (ISA), 1000 MHz clock rate, developed by MCST ;ELVEES * ELVEES Multicore – multicore hybrid of RISC and DSP ** 1892VM3T, (Russian: 1892ВМ3Т (MC-12)) – 1 ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Moscow Center Of SPARC Technologies (MCST)
MCST (russian: МЦСТ, acronym for Moscow Center of SPARC Technologies) is a Russian microprocessor company that was set up in 1992. Different types of processors made by MCST were used in personal computers, servers and computing systems. MCST develops microprocessors based on two different instruction set architecture (ISA): '' Elbrus'' and ''SPARC''. MCST is a direct descendant of the Lebedev Institute of Precision Mechanics and Computer Engineering. MCST is the base organization of the Department of Informatics and Computer Engineering of the Moscow Institute of Physics and Technology. MCST develops the Elbrus processor architecture and the eponymous family of universal VLIW microprocessors based on it with the participation of . The name "Elbrus" has been given the backronym "ExpLicit Basic Resources Utilization Scheduling". Products * '' Elbrus 1'' (1973) was the fourth generation Soviet computer, developed by Vsevolod Burtsev. Implements tag-based architecture and ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SPARC V9
SPARC (Scalable Processor Architecture) is a reduced instruction set computer (RISC) instruction set architecture originally developed by Sun Microsystems. Its design was strongly influenced by the experimental Berkeley RISC system developed in the early 1980s. First developed in 1986 and released in 1987, SPARC was one of the most successful early commercial RISC systems, and its success led to the introduction of similar RISC designs from many vendors through the 1980s and 1990s. The first implementation of the original 32-bit architecture (SPARC V7) was used in Sun's Sun-4 computer workstation and server systems, replacing their earlier Sun-3 systems based on the Motorola 68000 series of processors. SPARC V8 added a number of improvements that were part of the SuperSPARC series of processors released in 1992. SPARC V9, released in 1993, introduced a 64-bit architecture and was first released in Sun's UltraSPARC processors in 1995. Later, SPARC processors were used in sym ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Multiclet
MultiClet is an ongoing innovation project for a microprocessor that claims to be the first post von Neumann, multicellular microprocessor, breaking the paradigm for computing technology that has been in place for more than 60 years. There have been attempts in the past to shift away from the von Neumann architecture. Under MultiClet a 4-cellular dynamically reconfigurable microprocessor is implemented. History * In April 2013, the Russian company Sputnix signed an agreement for joint development of the MultiClet microprocessor. * In January 2014, an announcement is made that the FreeRTOS operating system has been ported to the MultiClet microprocessor, this demonstrates that the microprocessor potentially can perform tasks that makes it suitable for real products. * In April 2014, the Kickstarter project ''Key_P1 MultiClet: Your Powerful Digital Guardian'', failed to raise sufficient funding. * Since June 2014, the MultiClet microprocessor is reportedly under test in real space c ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
NeuroMatrix
NeuroMatrix is a digital signal processor (DSP) series developed by NTC Module. The DSP has a VLIW/SIMD architecture. It consists of a 32-bit RISC core and a 64-bit vector co-processor. The vector co-processor supports vector operations with elements of variable bit length (US Pat. 6539368 B1) and is optimized to support the implementation of artificial neural networks. From this derives the name NeuroMatrix Core (NMC). Newer devices contain multiple DSP cores and additional ARM or PowerPC 470 cores. Overview Details L1879VM1 * russian: Л1879ВМ1 * start of development in 1996, start of production in 1999 at Samsung 1879VM2 * russian: 1879ВМ2 * manufactured at Fujitsu 1879VM3 * russian: 1879ВМ3 * manufactured at Fujitsu 1879VM5Ya * russian: 1879ВМ5Я * manufactured at Fujitsu Japan 1879VM6Ya * russian: 1879ВМ6Я * manufactured at GlobalFoundries Malaysia 1879VM8Ya * russian: 1879ВМ8Я * system-on-a-chip (SoC) containing 4 computing clusters, each consistin ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
NTC Module
NTC Module (Research Center "Module") is a Russian scientific technological center (R&D production enterprise), founded in 1990 by the two enterprises of Russian military–industrial complex: NPO Vympel and NII Radiopriborostroyeniye. Conducting an applied researches in the field of digital pattern recognition technologies and the development of DSP and DIP hardware, constructing functionally complete computing complexes on this basis. Developer of a well-known microprocessor series NeuroMatrix. The embedded computers designed by NTC Module are used in the industrial, avionics and space applications including International Space Station. In particular, the MBC186 is installed at "Zarya Zarya may refer to: *Zorya, personification of dawn in Slavic mythology * Zarya (antenna), a type of medium-wave broadcasting antenna used in former Soviet Union *Zarya (ISS module) is a module of the International Space Station. * ''Zarya'' (magazi ..." module and the service module of ISS; "Y ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
MIPS IV
MIPS (Microprocessor without Interlocked Pipelined Stages) is a family of reduced instruction set computer (RISC) instruction set architectures (ISA)Price, Charles (September 1995). ''MIPS IV Instruction Set'' (Revision 3.2), MIPS Technologies, Inc. developed by MIPS Computer Systems, now MIPS Technologies, based in the United States. There are multiple versions of MIPS: including MIPS I, II, III, IV, and V; as well as five releases of MIPS32/64 (for 32- and 64-bit implementations, respectively). The early MIPS architectures were 32-bit; 64-bit versions were developed later. As of April 2017, the current version of MIPS is MIPS32/64 Release 6. MIPS32/64 primarily differs from MIPS I–V by defining the privileged kernel mode System Control Coprocessor in addition to the user mode architecture. The MIPS architecture has several optional extensions. MIPS-3D which is a simple set of floating-point SIMD instructions dedicated to common 3D tasks, MDMX (MaDMaX) which is a more extens ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
KOMDIV-64
The KOMDIV-64 (russian: КОМДИВ-64) is a family of 64-bit microprocessors developed by the Scientific Research Institute of System Development (NIISI) of the Russian Academy of Sciences and manufactured by TSMC, UMC, GlobalFoundries, and X-Fab. The KOMDIV-64 processors are primarily intended for industrial and high-performance computing applications. These microprocessors implement the MIPS IV instruction set architecture (ISA). Overview Nomenclature Many microprocessors listed here are following version 2000 of the soviet integrated circuit designation. Details 1990VM3T *0.35 μm CMOS process *240-pin QFP 1890VM5F *0.35 μm CMOS process *16 KB L1 instruction cache, 16 KB L1 data cache, 256 KB L2 cache *in-order, dual-issue superscalar; 5-stage integer pipeline, 7-stage floating point pipeline *26.6 million transistors *compatible with PMC-Sierra RM7000 *performance: 0.68 dhrystones/MHz, 1.03 whetstones/MHz, 1.09 coremarks/MHz 1890VM6Ya *0.18 μ ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
R3000
The R3000 is a 32-bit RISC microprocessor chipset developed by MIPS Computer Systems that implemented the MIPS I instruction set architecture (ISA). Introduced in June 1988, it was the second MIPS implementation, succeeding the R2000 as the flagship MIPS microprocessor. It operated at 20, 25 and 33.33 MHz. The MIPS 1 instruction set is small compared to those of the contemporary 80x86 and 680x0 architectures, encoding only more commonly used operations and supporting few addressing modes. Combined with its fixed instruction length and only three different types of instruction formats, this simplified instruction decoding and processing. It employed a 5-stage instruction pipeline, enabling execution at a rate approaching one instruction per cycle, unusual for its time. This MIPS generation supports up to four co-processors. In addition to the CPU core, the R3000 microprocessor includes a Control Processor (CP), which contains a Translation Lookaside Buffer and a Memory Manag ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
MIPS I
MIPS (Microprocessor without Interlocked Pipelined Stages) is a family of reduced instruction set computer (RISC) instruction set architectures (ISA)Price, Charles (September 1995). ''MIPS IV Instruction Set'' (Revision 3.2), MIPS Technologies, Inc. developed by MIPS Computer Systems, now MIPS Technologies, based in the United States. There are multiple versions of MIPS: including MIPS I, II, III, IV, and V; as well as five releases of MIPS32/64 (for 32- and 64-bit implementations, respectively). The early MIPS architectures were 32-bit; 64-bit versions were developed later. As of April 2017, the current version of MIPS is MIPS32/64 Release 6. MIPS32/64 primarily differs from MIPS I–V by defining the privileged kernel mode System Control Coprocessor in addition to the user mode architecture. The MIPS architecture has several optional extensions. MIPS-3D which is a simple set of floating-point SIMD instructions dedicated to common 3D tasks, MDMX (MaDMaX) which is a more extens ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
KOMDIV-32
The KOMDIV-32 (russian: КОМДИВ-32) is a family of 32-bit microprocessors developed and manufactured by the Scientific Research Institute of System Development (NIISI) of the Russian Academy of Sciences. The manufacturing plant of NIISI is located in Dubna on the grounds of the Kurchatov Institute. The KOMDIV-32 processors are intended primarily for spacecraft applications and many of them are radiation hardened (rad-hard). These microprocessors are compatible with MIPS R3000 and have an integrated MIPS R3010 compatible floating-point unit. Overview Details 1V812 *0.5 µm CMOS process, 3-layer metal * 108-pin ceramic Quad Flat Package (QFP) *1.5 million transistors, 8KB L1 instruction cache, 8KB L1 data cache, compatible with IDT 79R3081E 1890VM1T *0.5 µm CMOS process 1890VM2T *0.35 µm CMOS process 1990VM2T *0.35 µm silicon on insulator (SOI) CMOS process * 108-pin ceramic Quad Flat Package (QFP) * working temperature from -60 to 125 °C ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Scientific Research Institute Of System Development
Scientific Research Institute of System Analysis ( abbrev. SRISA/NIISI RAS, russian: НИИСИ РАН, russian: Научно-исследовательский институт системных исследований Российской Академии Наук) - is Russian state research and development institution in the field of complex applications, an initiative of the Russian Academy of Sciences. The mission of the institute is to resolve complex applied problems on the basis of fundamental and applied mathematics in combination with the methods of practical computing. Founded by the Decree no. 1174 of the Presidium of the USSR Academy of Sciences on October 1, 1986. Research fields Main lines of activities: * research in the field of theoretical and applied problems on information security, * research in the field of automation of programming, * research in the field of creating computer models of the objects with complex geometry and topology for the open scala ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
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