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Intel Socket G3
Socket G3, also known as rPGA 946B/947 or FCPGA 946, is a socket for Intel microprocessors that supports Haswell-based mobile CPUs. Compatible SKUs have an 'M' suffix in the model number. Socket G3 is designed as a replacement for the Socket G2, which is also known as rPGA 988B. Socket G3 has holes to make contact with 946 or 947 pins of the processor's pin grid array (PGA). Lynx Point is the Platform Controller Hub (PCH) associated with Socket G3. Socket rPGA 947 has one extra pin hole, other than that it is identical to socket G3. It is the last pin grid array socket for Intel's mobile processors - all mobile processors in microarchitectures succeeding Haswell are exclusively available in BGA packaging. Advanced Micro Devices also adopted same practice, starting with Steamroller microarchitecture. See also * List of Intel microprocessors * Micro-FCPGA * Socket G2 * Socket G1 * Socket P * Socket M Socket M (mPGA478MT) is a CPU interface introduced by Int ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Pin Grid Array
A pin grid array (PGA) is a type of integrated circuit packaging. In a PGA, the package is square or rectangular, and the pins are arranged in a regular array on the underside of the package. The pins are commonly spaced 2.54 mm (0.1") apart, and may or may not cover the entire underside of the package. PGAs are often mounted on printed circuit boards using the through hole method or inserted into a socket. PGAs allow for more pins per integrated circuit than older packages, such as dual in-line package (DIP). PGA variants Plastic Plastic pin grid array (PPGA) packaging was used by Intel for late-model Mendocino core Celeron processors based on Socket 370. Some pre-Socket 8 processors also used a similar form factor, although they were not officially referred to as PPGA. Flip chip A flip-chip pin grid array (FC-PGA or FCPGA) is a form of pin grid array in which the die faces downwards on the top of the substrate with the back of the die exposed. This allows ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Lynx Point
The Platform Controller Hub (PCH) is a family of Intel's single-chip chipsets, first introduced in 2009. It is the successor to the Intel Hub Architecture, which used two chips - a northbridge and southbridge, and first appeared in the Intel 5 Series. The PCH controls certain data paths and support functions used in conjunction with Intel CPUs. These include clocking (the system clock), Flexible Display Interface (FDI) and Direct Media Interface (DMI), although FDI is used only when the chipset is required to support a processor with integrated graphics. As such, I/O functions are reassigned between this new central hub and the CPU compared to the previous architecture: some northbridge functions, the memory controller and PCIe lanes, were integrated into the CPU while the PCH took over the remaining functions in addition to the traditional roles of the southbridge. AMD has its equivalent for the PCH, known simply as a chipset, no longer using the previous term Fusion control ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Socket P
The Intel Socket P (mPGA478MN) is the mobile processor socket replacement for Core microarchitecture chips such as Core 2 Duo. It launched on May 9, 2007, as part of the Santa Rosa platform with the Merom and Penryn processors. Technical specifications The front-side bus (FSB) of CPUs that install in Socket P can run at 400, 533, 667, 800, or 1066 MT/s. By adapting the multiplier the frequency of the CPU can throttle up or down to save power, given that all Socket P CPUs support EIST, except for Celeron that do not support EIST. Socket P has 478 pins, but is not electrically pin-compatible with Socket M or Socket 478. Socket P is also known as a 478-pin Micro FCPGA or μFCPGA-478. On the plastic grid is printed mPGA478MN. See also * List of Intel microprocessors * Micro-FCBGA A ball grid array (BGA) is a type of surface-mount packaging (a chip carrier) used for integrated circuits. BGA packages are used to permanently mount devices such as microprocessors. A BGA can pro ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Socket G1
Socket G1, also known as rPGA 988A, is a CPU socket introduced by Intel in 2009 for the mobile variants of the first-generation Intel Core processors. It is the successor to Socket P, and the mobile counterpart to LGA 1156 and LGA 1366. History The first CPUs for the Socket G1 platform were released on September 23, 2009, in the form of the i7-720QM, 820QM, and 920XM. These CPUs use the Clarksfield core, which maintained the same 45 nm manufacturing process as the desktop Nehalem architecture. On January 4, 2010, the range was expanded with Core i3, i5, and i7 processors using the 32 nm Arrandale core and based on the Westmere architecture. On March 28, 2010, low-end Arrandale-based CPUs were released as the Pentium P6x00 series and Celeron P4x00 series. Further Clarksfield-based processors were released as the i7-740QM, 840QM, and 940XM on June 21, 2010. All Socket G1 processors have the Intel HD Graphics Ironlake core packaged onto the CPU substrate. Supported processors ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Micro-FCPGA
Socket M (mPGA478MT) is a CPU interface introduced by Intel in 2006 for the Intel Core line of mobile processors. Technical specifications Socket M is used in all Intel Core products, as well as the Core-derived Dual-Core Xeon codenamed Sossaman. It was also used in the first generation of the mobile version of Intel's Core 2 Duo, specifically, the T5x00 and T7x00 Merom lines (referred to as Napa Refresh), though that line switched to Socket P (Santa Rosa) in 2007. It typically uses the Intel 945PM/945GM chipsets which support up to 667 MHz FSB and the Intel PM965/GM965 which allows 800 MHz FSB support, though the Socket M, PM965/GM965 combination is less common. The "Sossaman" Xeons use the E7520 chipset. Relation to other sockets Socket M is pin-compatible with desktop socket mPGA478A but it is not electrically compatible. Socket M is not pin-compatible with the older desktop Socket 478 (mPGA478B) or the newer mobile Socket P (mPGA478MN) by location of one pin; it i ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
List Of Intel Microprocessors
This generational list of Intel processors attempts to present all of Intel's processors from the pioneering 4-bit 4004 (1971) to the present high-end offerings. Concise technical data is given for each product. Latest 13th generation Core Desktop (codenamed "Raptor Lake") 12th generation Core Desktop (codenamed "Alder Lake") Mobile (codenamed "Alder Lake") 11th generation Core Desktop (codenamed "Rocket Lake") Mobile (codenamed "Tiger Lake") 10th generation Core Desktop (codenamed "Comet Lake") Mobile (codenamed "Comet Lake", " Ice Lake", and " Amber Lake") 9th generation Core Desktop (codenamed "Coffee Lake Refresh") 8th generation Core Desktop (codenamed "Coffee Lake") Mobile (codenamed "Coffee Lake", " Amber Lake" and " Whiskey Lake") 7th generation Core Desktop (codenamed "Kaby Lake" and "Skylake-X") Mobile (codenamed "Kaby Lake" and " Apollo Lake") All processors All processors are listed in chron ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Steamroller (microarchitecture)
AMD Steamroller Family 15h is a microarchitecture developed by AMD for AMD APUs, which succeeded Piledriver in the beginning of 2014 as the third-generation Bulldozer-based microarchitecture. Steamroller APUs continue to use two-core modules as their predecessors, while aiming at achieving greater levels of parallelism. Microarchitecture ''Steamroller'' still features two-core modules found in ''Bulldozer'' and ''Piledriver'' designs called clustered multi-thread (CMT), meaning that one module is marketed as a dual-core processor. The focus of ''Steamroller'' is for greater parallelism. Improvements center on independent instruction decoders for each core within a module, 25% more of the maximum width dispatches per thread, better instruction schedulers, improved perceptron branch predictor, larger and smarter caches, up to 30% fewer instruction cache misses, branch misprediction rate reduced by 20%, dynamically resizable L2 cache, micro-operations queue, more internal regist ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Advanced Micro Devices
Advanced Micro Devices, Inc. (AMD) is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets. While it initially manufactured its own processors, the company later outsourced its manufacturing, a practice known as going fabless, after GlobalFoundries was spun off in 2009. AMD's main products include microprocessors, motherboard chipsets, embedded processors, graphics processors, and FPGAs for servers, workstations, personal computers, and embedded system applications. History First twelve years Advanced Micro Devices was formally incorporated by Jerry Sanders, along with seven of his colleagues from Fairchild Semiconductor, on May 1, 1969. Sanders, an electrical engineer who was the director of marketing at Fairchild, had, like many Fairchild executives, grown frustrated with the increasing lack of support, opportunity, and flexibility within th ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Ball Grid Array
A ball grid array (BGA) is a type of surface-mount packaging (a chip carrier) used for integrated circuits. BGA packages are used to permanently mount devices such as microprocessors. A BGA can provide more interconnection pins than can be put on a dual in-line or flat package. The whole bottom surface of the device can be used, instead of just the perimeter. The traces connecting the package's leads to the wires or balls which connect the die to package are also on average shorter than with a perimeter-only type, leading to better performance at high speeds. BGAs were introduced in the 1990s and became popular by 2001. Soldering of BGA devices requires precise control and is usually done by automated processes such as in computer-controlled automatic reflow ovens. Description The BGA is descended from the pin grid array (PGA), which is a package with one face covered (or partly covered) with pins in a grid pattern which, in operation, conduct electrical signals betwe ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Platform Controller Hub
The Platform Controller Hub (PCH) is a family of Intel's single-chip chipsets, first introduced in 2009. It is the successor to the Intel Hub Architecture, which used two chips - a Northbridge (computing), northbridge and Southbridge (computing), southbridge, and first appeared in the Intel 5 Series. The PCH controls certain data paths and support functions used in conjunction with Intel CPUs. These include clocking (the system clock), Flexible Display Interface (FDI) and Direct Media Interface (DMI), although FDI is used only when the chipset is required to support a processor with integrated graphics. As such, I/O functions are reassigned between this new central hub and the CPU compared to the previous architecture: some northbridge functions, the memory controller and PCI Express, PCIe lanes, were integrated into the CPU while the PCH took over the remaining functions in addition to the traditional roles of the southbridge. AMD has its equivalent for the PCH, known simply as a ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Microprocessor
A microprocessor is a computer processor where the data processing logic and control is included on a single integrated circuit, or a small number of integrated circuits. The microprocessor contains the arithmetic, logic, and control circuitry required to perform the functions of a computer's central processing unit. The integrated circuit is capable of interpreting and executing program instructions and performing arithmetic operations. The microprocessor is a multipurpose, clock-driven, register-based, digital integrated circuit that accepts binary data as input, processes it according to instructions stored in its memory, and provides results (also in binary form) as output. Microprocessors contain both combinational logic and sequential digital logic, and operate on numbers and symbols represented in the binary number system. The integration of a whole CPU onto a single or a few integrated circuits using Very-Large-Scale Integration (VLSI) greatly reduced the cost of ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Direct Media Interface
In computing, Direct Media Interface (DMI) is Intel's proprietary link between the northbridge and southbridge on a computer motherboard. It was first used between the 9xx chipsets and the ICH6, released in 2004. Previous Intel chipsets had used the Intel Hub Architecture to perform the same function, and server chipsets use a similar interface called ''Enterprise Southbridge Interface'' (ESI). While the "DMI" name dates back to ICH6, Intel mandates specific combinations of compatible devices, so the presence of a DMI interface does not guarantee by itself that a particular northbridge–southbridge combination is allowed. DMI shares many characteristics with PCI Express, using multiple lanes and differential signaling to form a point-to-point link. Most implementations use a ×4 link, while some mobile systems (e.g. 915GMS, 945GMS/GSE/GU and the Atom N450) use a ×2 link, halving the bandwidth. The original implementation provides 10 Gbit/s (1 GB/s) in each di ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
_CPU-pins_PNr°0295.jpg "Click for more on -> Pin Grid Array")
