Scan chain

Scan chain is a technique used in design for testing (DFT). The objective is to make testing easier by providing a simple way to set and observe every flip-flop in an IC. It simplifies the testing and debugging of complex digital systems. In scan-based design, flip-flops operate in two distinct modes: normal mode and scan mode. In normal mode, they support regular system operations. In scan mode, however, they are reconfigured into one long shift register, known as a Scan Chain.

The basic structure of scan include the following set of signals in order to control and observe the scan mechanism.

1. Scan_in (SI) and Scan_out (SO) define the input and output of a scan chain. In a full scan mode usually each input drives only one chain and scan out observe one as well.
2. A scan enable (SE) pin is a special signal that is added to a design. When this signal is asserted, every flip-flop in the design is connected into a long shift register.
3. Clock signal which is used for controlling all the flip-flops in the chain during shift phase and the capture phase. An arbitrary pattern can be entered into the chain of flip-flops, and the state of every flip-flop can be read out.