Design flow

Suite of electronic design tools Design flows, often known as RTL to GDSII, are the explicit combination of electronic design automation tools to accomplish the design of an integrated circuit. They start with a textual description of the proposed chip operation, written in a register transfer level (RTL) language such as Verilog. These are converted to a netlist by a logic synthesis tool, and the resulting gates are then placed, and routed. The result is an image of the chip to be fabricated, typically in the GDSII format. History In the early days of chips, up until the mid 1970s, each step in a design flow was done by hand. Engineers drew logic diagrams to express the chip function, decided where to place each gate on the chip, and drew wires to interconnect the gates. As chips became larger at a rate determined by Moore's law, manual design became impractically slow and error prone. This first led to stand-alone tools such as synthesis, placement, and routing, each of which tackled part of the problem. However interactions between the tools, and the importance of new effects such as interconnect delay and design for manufacturability, led to the need to integrate these tools in