Topic summary
Clock distribution network
Extracted from the Wikipedia article Clock signal.
Further reading
- Eby G. Friedman (Ed.), Clock Distribution Networks in VLSI Circuits and Systems, ISBN , IEEE Press. 1995.
- Eby G. Friedman, Clock Distribution Networks in Synchronous Digital Integrated Circuits", Proceedings of the IEEE, Vol. 89, No. 5, pp. 665–692, May 2001. doi:10.1109/5.929649
- "ISPD 2010 High Performance Clock Network Synthesis Contest", International Symposium on Physical Design, Intel, IBM, 2010.
- D.-J. Lee, "High-performance and Low-power Clock Network Synthesis in the Presence of Variation", Ph.D. dissertation, University of Michigan, 2011.
- I. L. Markov, D.-J. Lee, "Algorithmic Tuning of Clock Trees and Derived Non-Tree Structures", in Proc. Int'l. Conf. Comp.-Aided Design (ICCAD), 2011.
- V. G. Oklobdzija, V. M. Stojanovic, D. M. Markovic, and N. M. Nedovic, Digital System Clocking: High-Performance and Low-Power Aspects, ISBN , IEEE Press/Wiley-Interscience, 2003.
- Mitch Dale, "The power of RTL Clock-gating", Electronic Systems Design Engineering Incorporating Chip Design, January 20, 2007.