List of cache coherency protocols

Examples of coherency protocols for cache memory are listed here. For simplicity, all "miss" Read and Write status transactions, which all only come from state "I" ("invalid", or miss of Tag), in the diagrams are not shown. They are shown directly on the new state. Many of the following protocols have only historical value. At the moment the main protocols used are the R-MESI type / MESIF protocols and the HRT-ST-MESI (MOESI type) or a subset or an extension of these. Cache coherency problem In systems such as Multiprocessor, multi-core and NUMA systems, where a dedicated cache exists for each processor, core or node, a consistency problem may occur when the same piece of data is (copied and) stored in more than one cache. This problem arises when the data value is modified in one cache but has not been modified in the other caches, leading to an unknown "ground truth" value of the piece of data across the entire system, where each cache's version of the piece of data is treated as equally valid. This problem can be solved in two ways: Invalidate all the copies on other caches ("broadcast-invalidate") Update all the copies on other caches (write-broadcasting) to the new correct val