Topic summary
AMD K10
Extracted from the Wikipedia article AMD 10h.
Agena (65 nm SOI, quad-core)
- Four AMD K10 cores
- L1 cache: 64 KB instruction and 64 KB data (data + instructions) per core
- L2 cache: 512 KB per core, full-speed
- L3 cache: 2 MB shared between all cores
- Memory controller: dual channel DDR2-1066 MHz with unganging option
- ISA extensions: MMX, Enhanced 3DNow!, SSE, SSE2, SSE3, SSE4a, ABM, AMD64, NX bit, AMD-V
- Power management features: Cool'n'Quiet
- Socket AM2+, HyperTransport with 1600 to 2000 MHz
- Power consumption (TDP): 65, 95, 125 and 140 Watt
- First release
- November 19, 2007 (B2 Stepping)
- March 27, 2008 (B3 Stepping)