7 nm process

MOSFET technology node Semiconductordevicefabrication MOSFET scaling(process nodes) 020 μm – 1968 010 μm – 1971 006 μm – 1974 003 μm – 1977 1.5 μm – 1981 001 μm – 1984 800 nm – 1987 600 nm – 1990 350 nm – 1993 250 nm – 1996 180 nm – 1999 130 nm – 2001 090 nm – 2003 065 nm – 2005 045 nm – 2007 032 nm – 2009 028 nm – 2010 022 nm – 2012 014 nm – 2014 010 nm – 2016 007 nm – 2018 005 nm – 2020 003 nm – 2022 002 nm – 2025 Future 001 nm ~ 2027 Half-nodes Density CMOS Device (multi-gate) Moore's law Transistor count Semiconductor Industry Nanoelectronics vte In semiconductor manufacturing, the "7 nm" process is a term for the MOSFET technology node following the "10 nm" node, defined by the International Roadmap for Devices and Systems (IRDS), which was preceded by the International Technology Roadmap for Semiconductors (ITRS). It is based on FinFET (fin field-effect transistor) technology, a type of multi-gate MOSFET technology. As of 2021, the IRDS Lithography standard gives a table of dimensions for the "7 nm" node, with examples given below: Calculated Value nm Minimum half pitch (DRAM, MPU metal) 18 Minimum half pitch (Flash, MPU f