A single cycle processor is a processor that carries out one instruction in a single
clock cycle.
See also
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Complex instruction set computer
A complex instruction set computer (CISC ) is a computer architecture in which single instructions can execute several low-level operations (such as a load from memory, an arithmetic operation, and a memory store) or are capable of multi-step ...
, a processor executing one instruction in multiple clock cycles
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DLX, a very similar architecture designed by
John L. Hennessy (creator of MIPS) for teaching purposes
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MIPS architecture
MIPS (Microprocessor without Interlocked Pipelined Stages) is a family of reduced instruction set computer (RISC) instruction set architectures (ISA)Price, Charles (September 1995). ''MIPS IV Instruction Set'' (Revision 3.2), MIPS Technologies ...
, MIPS-32 architecture
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MIPS-X
MIPS-X is a reduced instruction set computer (RISC) microprocessor and instruction set architecture (ISA) developed as a follow-on project to the Stanford MIPS, MIPS project at Stanford University by the same team that developed MIPS. The project ...
, developed as a follow-on project to the MIPS architecture
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Reduced instruction set computer
In electronics and computer science, a reduced instruction set computer (RISC) is a computer architecture designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a com ...
, a processor executing one instruction in minimal clock cycles
References
External links
Microprocessors
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