The Runway bus is a

front-side bus The front-side bus (FSB) is a computer communication interface ( bus) that was often used in Intel-chip-based computers during the 1990s and 2000s. The EV6 bus served the same function for competing AMD CPUs. Both typically carry data between th ...

developed by

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for use by its

PA-RISC Precision Architecture reduced instruction set computer, RISC (PA-RISC) or Hewlett Packard Precision Architecture (HP/PA or simply HPPA), is a computer, general purpose computer instruction set architecture (ISA) developed by Hewlett-Packard f ...

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family. The Runway bus is a 64-bit wide, split transaction, time multiplexed address and data bus running at 120 MHz. This scheme was chosen by HP as they determined that a bus using separate address and data wires would have only delivered 20% more bandwidth for a 50% increase in pin count, which would have made microprocessors using the bus more expensive. The Runway bus was introduced with the release of the PA-7200 and was subsequently used by the

PA-8000 The PA-8000 (PCX-U), code-named ''Onyx'', is a microprocessor developed and fabricated by Hewlett-Packard (HP) that implemented the PA-RISC, PA-RISC 2.0 instruction set architecture (ISA).#Hunt_1995, Hunt 1995 It was a completely new design with ...

, PA-8200, PA-8500, PA-8600 and PA-8700 microprocessors. Early implementations of the bus used in the PA-7200, PA-8000 and PA-8200 had a theoretical bandwidth of 960 MB/s. Beginning with the PA-8500, the Runway bus was revised to transmit on both rising and falling edges of a 125 MHz clock signal, which increased its theoretical bandwidth to 2 GB/s. The Runway bus was succeeded with the introduction of the PA-8800, which used the

Itanium 2 Itanium (; ) is a discontinued family of 64-bit Intel microprocessors that implement the Intel Itanium architecture (formerly called IA-64). The Itanium architecture originated at Hewlett-Packard (HP), and was later jointly developed by HP and I ...

bus. Bus features * 64-bit multiplexed address/data * 20 bus protocol signals * Supports cache coherency * Three frequency options (1.0, 0.75 and 0.67 of CPU clock — 0.50 apparently was later added) * Parity protection on address/data and control signal * Each attached device contains its own arbitrator logic * Split transactions, up to six transactions can be pending at once * Snooping cache coherency protocol * 1-4 processors "glueless" multi-processing (no support chips needed) * 768 MB/s sustainable throughput, peak 960 MB/s at 120 MHz * Runway+/Runway DDR: On PA-8500, PA-8600 and PA-8700, the bus operates in DDR (double data rate) mode, * resulting in a peak bandwidth of about 2.0 GB/s (Runway+ or Runway DDR) with 125 MHz Most machines use the Runway bus to connect the CPUs directly to the IOMMU (Astro, U2/Uturn or Java) and memory. However, the N class and L3000 servers use an interface chip called Dew to bridge the Runway bus to the Merced bus that connects to the IOMMU and

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References

* * Gwennap, Linley (November 17, 1997). "PA-8500's 1.5M Cache Aids Performance". ''

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''. {{Computer-bus Hewlett-Packard products Computer buses