A unified reservation station, also known as unified scheduler, is a decentralized feature of the

microarchitecture In computer engineering, microarchitecture, also called computer organization and sometimes abbreviated as µarch or uarch, is the way a given instruction set architecture (ISA) is implemented in a particular processor. A given ISA may be imp ...

of a

CPU A central processing unit (CPU), also called a central processor, main processor or just processor, is the electronic circuitry that executes instructions comprising a computer program. The CPU performs basic arithmetic, logic, controlling, an ...

that allows for

register renaming In computer architecture, register renaming is a technique that abstracts logical registers from physical registers. Every logical register has a set of physical registers associated with it. When a machine language instruction refers to a partic ...

, and is used by the

Tomasulo algorithm Tomasulo's algorithm is a computer architecture hardware algorithm for dynamic scheduling of instructions that allows out-of-order execution and enables more efficient use of multiple execution units. It was developed by Robert Tomasulo at IBM i ...

for dynamic instruction scheduling. Reservation stations permit the CPU to fetch and re-use a data value as soon as it has been computed, rather than waiting for it to be stored in a register and re-read. When instructions are issued, they can designate the reservation station from which they want their input to read. When multiple instructions need to write to the same register, all can proceed and only the (logically) last one need actually be written. It checks if the operands are available ( RAW) and if execution unit is free (

Structural hazard In the domain of central processing unit (CPU) design, hazards are problems with the instruction pipeline in CPU microarchitectures when the next instruction cannot execute in the following clock cycle, and can potentially lead to incorrect compu ...

) before starting execution. Instructions are stored with available parameters, and executed when ready. Results are identified by the unit that will execute the corresponding instruction. Implicitly register renaming solves

WAR War is an intense armed conflict between states, governments, societies, or paramilitary groups such as mercenaries, insurgents, and militias. It is generally characterized by extreme violence, destruction, and mortality, using regular o ...

and WAW hazards. Since this is a fully associative structure, it has a very high cost in comparators (need to compare all results returned from processing units with all stored addresses). In Tomasulo's algorithm, instructions are issued in sequence to Reservation Stations which buffer the instruction as well as the operands of the instruction. If the operand is not available, the Reservation Station listens on a Common Data Bus for the operand to become available. When the operand becomes available, the Reservation Station buffers it, and the execution of the instruction can begin. Functional Units (such as an adder or a multiplier), each have their own corresponding Reservation Stations. The output of the Functional Unit connects to the Common Data Bus, where Reservation Stations are listening for the operands they need.

Bibliography

Computer Architecture: A Quantitative Approach
John L. Hennessy, David A. Patterson, 2012 () "3.4 Overcoming Data Hazards with Dynamic Scheduling", p 172-180

References

External links

HASE Project, Institute for Computing Systems Architecture, School of Informatics, University of Edinburgh, 2003
CS6290 Tomasulo’s Algorithm
{{Webarchive, url=https://web.archive.org/web/20141208160924/http://www.cc.gatech.edu/fac/milos/Teaching/CS6290F07/4_Tomasulo.pdf , date=2014-12-08 , Georgia Tech Instruction processing