RISC-V assembly language is a

low-level programming language A low-level programming language is a programming language that provides little or no Abstraction (computer science), abstraction from a computer's instruction set architecture, memory or underlying physical hardware; commands or functions in the ...

that is used to produce

object code In computing, object code or object module is the product of an assembler or compiler In computing, a compiler is a computer program that Translator (computing), translates computer code written in one programming language (the ''source'' ...

for the

RISC-V RISC-V (pronounced "risk-five") is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. The project commenced in 2010 at the University of California, Berkeley. It transfer ...

class of processors. Assembly languages are closely tied to the architecture's machine code instructions, allowing for precise control over hardware. Assemblers include

GNU Assembler The GNU Assembler, commonly known as gas or as, is the assembler developed by the GNU Project. It is the default back-end of GCC. It is used to assemble the GNU operating system and the Linux kernel, and various other software. It is a part o ...

and

LLVM LLVM, also called LLVM Core, is a target-independent optimizer and code generator. It can be used to develop a Compiler#Front end, frontend for any programming language and a Compiler#Back end, backend for any instruction set architecture. LLVM i ...

Keywords

Reserved keywords of RISC-V assembly language.

Mnemonics and opcodes

Each instruction in the RISC-V assembly language is represented by a

mnemonic A mnemonic device ( ), memory trick or memory device is any learning technique that aids information retention or retrieval in the human memory, often by associating the information with something that is easier to remember. It makes use of e ...

which often combines with one or more operands to translate into one or more bytes known as an

opcode In computing, an opcode (abbreviated from operation code) is an enumerated value that specifies the operation to be performed. Opcodes are employed in hardware devices such as arithmetic logic units (ALUs), central processing units (CPUs), and ...

Registers

RISC-V processors feature a set of registers that serve as storage for binary data and addresses during program execution. These registers are categorized into integer registers and floating-point registers.

Instruction types

RISC-V instructions use variable-length encoding. Extensions: * atomic instructions * single-precision floating-point * double-precision floating-point * bit manipulation * cryptography * hypervisor * supervisor * packed-SIMD instructions * vector

Floating-point instructions

RISC-V assembly language includes instructions for a

floating-point unit A floating-point unit (FPU), numeric processing unit (NPU), colloquially math coprocessor, is a part of a computer system specially designed to carry out operations on floating-point numbers. Typical operations are addition, subtraction, multip ...

(FPU).

SIMD instructions

These largely perform the same operation in parallel on many values.

Program flow

The RISC-V assembly has conditional branch instructions based on comparison: (equal), (not equal), (less than, signed), (less than, unsigned), (greater than or equal, signed), and (greater than or equal, unsigned).

Examples

.section .text .globl _start _start: lui a1, %hi(msg) # load msg(hi) addi a1, a1, %lo(msg) # load msg(lo) jalr ra, puts 2: j 2b .section .rodata msg: .string "Hello World\n"

External links

Ripes
A graphical processor simulator and assembly editor
venus
A instruction set simulator () * {{RISC-V Articles with example code Assembly languages RISC-V