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I2C (Inter-Integrated Circuit; pronounced as "" or ""), alternatively known as I2C and IIC, is a synchronous, multi-master/multi-slave, single-ended, serial communication bus invented in 1980 by Philips Semiconductors (now
NXP Semiconductors NXP Semiconductors N.V. is a Dutch semiconductor manufacturing and design company with headquarters in Eindhoven, Netherlands. It is the third largest European semiconductor company by market capitalization as of 2024. The company employs approx ...
). It is widely used for attaching lower-speed peripheral
integrated circuits An integrated circuit (IC), also known as a microchip or simply chip, is a set of electronic circuits, consisting of various electronic components (such as transistors, resistors, and capacitors) and their interconnections. These components a ...
(ICs) to processors and
microcontroller A microcontroller (MC, uC, or μC) or microcontroller unit (MCU) is a small computer on a single integrated circuit. A microcontroller contains one or more CPUs (processor cores) along with memory and programmable input/output peripherals. Pro ...
s in short-distance, intra-board communication. The I2C bus can be found in a wide range of electronics applications where simplicity and low manufacturing cost are more important than speed. PC components and systems which involve I2C include
serial presence detect In computing, serial presence detect (SPD) is a standardized way to automatically access information about a memory module. Earlier 72-pin SIMMs included five pins that provided five bits of ''parallel presence detect'' (PPD) data, but the 168- ...
(SPD) EEPROMs on
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s (DIMMs) and Extended Display Identification Data (EDID) for monitors via VGA, DVI, and
HDMI High-Definition Multimedia Interface (HDMI) is a proprietary digital interface used to transmit high-quality video and audio signals between devices. It is commonly used to connect devices such as televisions, computer monitors, projectors, gam ...
connectors. Common I2C applications include reading hardware monitors, sensors, real-time clocks, controlling actuators, accessing low-speed DACs and ADCs, controlling simple LCD or OLED displays, changing
computer display A computer monitor is an output device that displays information in pictorial or textual form. A discrete monitor comprises a visual display, support electronics, power supply, housing, electrical connectors, and external user controls. T ...
settings (e.g., backlight, contrast, hue, color balance) via Display Data Channel, and changing speaker volume. A particular strength of I2C is the capability of a
microcontroller A microcontroller (MC, uC, or μC) or microcontroller unit (MCU) is a small computer on a single integrated circuit. A microcontroller contains one or more CPUs (processor cores) along with memory and programmable input/output peripherals. Pro ...
to control a network of device chips with just two general-purpose I/O pins and software. Many other bus technologies used in similar applications, such as Serial Peripheral Interface Bus (SPI), require more pins and signals to connect multiple devices. System Management Bus (SMBus), defined by Intel and Duracell in 1994, is a subset of I2C, defining a stricter usage. One purpose of SMBus is to promote robustness and interoperability. Accordingly, modern I2C systems incorporate some policies and rules from SMBus, sometimes supporting both I2C and SMBus, requiring only minimal reconfiguration either by commanding or output pin use. System management for PC systems uses SMBus whose pins are allocated in both conventional PCI and
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe, is a high-speed standard used to connect hardware components inside computers. It is designed to replace older expansion bus standards such as Peripher ...
connectors.


Terminology

I2C patents and specifications used the terms '' master/slave'' between 1980 and 2021. In 2021, revision 7 of the I2C specification changed the terms to ''controller/target''. The technical definitions of such devices, and their roles on an I2C bus, remain unchanged.


Design

I2C uses only two signals: serial data line (SDA) and serial clock line (SCL). Both are bidirectional and pulled up with
resistor A resistor is a passive two-terminal electronic component that implements electrical resistance as a circuit element. In electronic circuits, resistors are used to reduce current flow, adjust signal levels, to divide voltages, bias active e ...
s. Typical voltages used are +5  V or +3.3 V, although systems with other voltages are permitted. The I2C reference design has a 7-bit
address space In computing, an address space defines a range of discrete addresses, each of which may correspond to a network host, peripheral device, disk sector, a memory cell or other logical or physical entity. For software programs to save and retrieve ...
, with a rarely used 10-bit extension. Common I2C bus speeds are the ''standard mode'' and the ''fast mode''. There is also a ''low-speed mode'', but arbitrarily low clock frequencies are also allowed. Later revisions of I2C can host more nodes and run at faster speeds ( ''fast mode'', ''fast mode plus'', ''high-speed mode'', and ''ultra-fast mode''). These speeds are more widely used on embedded systems than on PCs. Note that the bit rates are quoted for the transfers between controller (master) and target (slave) without clock stretching or other hardware overhead. Protocol overheads include a target address and perhaps a register address within the target device, as well as per-byte ACK/NACK bits. Thus the actual transfer rate of user data is lower than those peak bit rates alone would imply. For example, if each interaction with a target inefficiently allows only 1 byte of data to be transferred, the data rate will be less than half the peak bit rate. The number of nodes which can exist on a given I2C bus is limited by the address space and also by the total bus
capacitance Capacitance is the ability of an object to store electric charge. It is measured by the change in charge in response to a difference in electric potential, expressed as the ratio of those quantities. Commonly recognized are two closely related ...
of 400  pF, which restricts practical communication distances to a few meters. The relatively high impedance and low noise immunity requires a common ground potential, which again restricts practical use to communication within the same PC board or small system of boards.


Reference design

The aforementioned reference design is a bus with a
clock A clock or chronometer is a device that measures and displays time. The clock is one of the oldest Invention, human inventions, meeting the need to measure intervals of time shorter than the natural units such as the day, the lunar month, a ...
(SCL) and data (SDA) lines with 7-bit addressing. The bus has two roles for nodes, either controller (master) or target (slave): * Controller (master) node: Node that generates the clock and initiates communication with targets (slaves). * Target (slave) node: Node that receives the clock and responds when addressed by the controller (master). The bus is a multi-controller bus, which means that any number of controller nodes can be present. Additionally, controller and target roles may be changed between messages (after a STOP is sent). There may be four potential modes of operation for a given bus device, although most devices only use a single role and its two modes: * Controller (master) transmit: Controller node is sending data to a target (slave). * Controller (master) receive: Controller node is receiving data from a target (slave). * Target (slave) transmit: Target node is sending data to the controller (master). * Target (slave) receive: Target node is receiving data from the controller (master). In addition to 0 and 1 data bits, the I2C bus allows special START and STOP signals which act as message delimiters and are distinct from the data bits. (This is in contrast to the start bits and
stop bit Asynchronous serial communication is a form of serial communication in which the communicating endpoints' interfaces are not continuously synchronized by a common clock signal. Synchronization ( clock recovery) is done by data-embedded signal ...
s used in asynchronous serial communication, which are distinguished from data bits only by their timing.) The controller is initially in controller transmit mode by sending a START followed by the 7-bit address of the target it wishes to communicate with, which is finally followed by a single bit representing whether it wishes to write (0) to or read (1) from the target. If the target exists on the bus then it will respond with an ACK bit (active low for acknowledged) for that address. The controller then continues in either transmit or receive mode (according to the read/write bit it sent), and the target continues in the complementary mode (receive or transmit, respectively). The address and the data bytes are sent
most significant bit In computing, bit numbering is the convention used to identify the bit positions in a binary numeral system, binary number. Bit significance and indexing In computing, the least significant bit (LSb) is the bit position in a Binary numeral sy ...
first. The start condition is indicated by a high-to-low transition of SDA with SCL high; the stop condition is indicated by a low-to-high transition of SDA with SCL high. All other transitions of SDA take place with SCL low. If the controller wishes to write to the target, then it repeatedly sends a byte with the target sending an ACK bit. (In this situation, the controller is in controller transmit mode, and the target is in target receive mode.) If the controller wishes to read from the target, then it repeatedly receives a byte from the target, the controller sending an ACK bit after every byte except the last one. (In this situation, the controller is in controller receive mode, and the target is in target transmit mode.) An I2C transaction may consist of multiple messages. The controller terminates a message with a STOP condition if this is the end of the transaction or it may send another START condition to retain control of the bus for another message (a "combined format" transaction).


Message protocols

I2C defines basic types of transactions, each of which begins with a START and ends with a STOP: * Single message where a controller (master) writes data to a target (slave). * Single message where a controller (master) reads data from a target (slave). * Combined format, where a controller (master) issues at least two reads or writes to one or more targets (slaves). In a combined transaction, each read or write begins with a START and the target address. The START conditions after the first are also called ''repeated START'' bits. Repeated STARTs are not preceded by STOP conditions, which is how targets know that the next message is part of the same transaction. Any given target will only respond to certain messages, as specified in its product documentation. Pure I2C systems support arbitrary message structures. SMBus is restricted to nine of those structures, such as ''read word N'' and ''write word N'', involving a single target. PMBus extends SMBus with a ''Group'' protocol, allowing multiple such SMBus transactions to be sent in one combined message. The terminating STOP indicates when those grouped actions should take effect. For example, one PMBus operation might reconfigure three power supplies (using three different I2C target addresses), and their new configurations would take effect at the same time: when they receive that STOP. With only a few exceptions, neither I2C nor SMBus define message semantics, such as the meaning of data bytes in messages. Message semantics are otherwise product-specific. Those exceptions include messages addressed to the I2C ''general call'' address (0x00) or to the SMBus ''Alert Response Address''; and messages involved in the SMBus ''Address Resolution Protocol'' (ARP) for dynamic address allocation and management. In practice, most targets adopt request-response control models, where one or more bytes following a write command are treated as a command or address. Those bytes determine how subsequent written bytes are treated or how the target responds on subsequent reads. Most SMBus operations involve single-byte commands.


Messaging example: 24C32 EEPROM

One specific example is the 24C32 type EEPROM, which uses two request bytes that are called Address High and Address Low. (Accordingly, these EEPROMs are not usable by pure SMBus hosts, which support only single-byte commands or addresses.) These bytes are used for addressing bytes within the 32  kbit (or 4  kB) EEPROM address space. The same two-byte addressing is also used by larger EEPROMs, like the 24C512 which stores 512 kbits (or 64 kB). Writing data to and reading from these EEPROMs uses a simple protocol: the address is written, and then data is transferred until the end of the message. The data transfer part of the protocol can cause trouble on the SMBus, since the data bytes are not preceded by a count, and more than 32 bytes can be transferred at once. I2C EEPROMs smaller than 32 kbit, like the 2 kbit 24C02, are often used on the SMBus with inefficient single-byte data transfers to overcome this problem. A single message writes to the EEPROM. After the START, the controller sends the chip's bus address with the direction bit clear (''write''), then sends the two-byte address of data within the EEPROM and then sends data bytes to be written starting at that address, followed by a STOP. When writing multiple bytes, all the bytes must be in the same 32-byte page. While it is busy saving those bytes to memory, the EEPROM will not respond to further I2C requests. (That is another incompatibility with SMBus: SMBus devices must always respond to their bus addresses.) To read starting at a particular address in the EEPROM, a combined message is used. After a START, the controller first writes that chip's bus address with the direction bit clear (''write'') and then the two bytes of EEPROM data address. It then sends a (repeated) START and the EEPROM's bus address with the direction bit set (''read''). The EEPROM will then respond with the data bytes beginning at the specified EEPROM data address — a combined message: first a write, then a read. The controller issues an ACK after each read byte except the last byte, and then issues a STOP. The EEPROM increments the address after each data byte transferred; multi-byte reads can retrieve the entire contents of the EEPROM using one combined message.


Physical layer

At the
physical layer In the seven-layer OSI model of computer networking, the physical layer or layer 1 is the first and lowest layer: the layer most closely associated with the physical connection between devices. The physical layer provides an electrical, mechani ...
, both SCL and SDA lines are an open-drain (
MOSFET upright=1.3, Two power MOSFETs in amperes">A in the ''on'' state, dissipating up to about 100 watt">W and controlling a load of over 2000 W. A matchstick is pictured for scale. In electronics, the metal–oxide–semiconductor field- ...
) or open-collector ( BJT) bus design, thus a
pull-up resistor In electronic logic circuits, a pull-up resistor (PU) or pull-down resistor (PD) is a resistor used to ensure a known state for a signal. More specifically, a pull-up resistor or pull-down resistor ensures that a wire will have a high logic lev ...
is needed for each line. A logic "0" is output by pulling the line to ground, and a logic "1" is output by letting the line float (output high impedance) so that the pull-up resistor pulls it high. A line is never actively driven high. This wiring allows multiple nodes to connect to the bus without short circuits from signal contention. High-speed systems (and some others) may use a current source instead of a resistor to pull-up only SCL or both SCL and SDA, to accommodate higher bus capacitance and enable faster rise times. An important consequence of this is that multiple nodes may be driving the lines simultaneously. If ''any'' node is driving the line low, it will be low. Nodes that are trying to transmit a logical one (i.e. letting the line float high) can detect this and conclude that another node is active at the same time. When used on SCL, this is called ''clock stretching'' and is a flow-control mechanism for targets. When used on SDA, this is called
arbitration Arbitration is a formal method of dispute resolution involving a third party neutral who makes a binding decision. The third party neutral (the 'arbitrator', 'arbiter' or 'arbitral tribunal') renders the decision in the form of an 'arbitrati ...
and ensures that there is only one transmitter at a time. When idle, both lines are high. To start a transaction, SDA is pulled low while SCL remains high. It is illegal to transmit a stop marker by releasing SDA to float high again (although such a "void message" is usually harmless), so the next step is to pull SCL low. Except for the start and stop signals, the SDA line only changes while the clock is low; transmitting a data bit consists of pulsing the clock line high while holding the data line steady at the desired level. While SCL is low, the transmitter (initially the controller) sets SDA to the desired value and (after a small delay to let the value propagate) lets SCL float high. The controller then waits for SCL to actually go high; this will be delayed by the finite rise time of the SCL signal (the RC time constant of the
pull-up resistor In electronic logic circuits, a pull-up resistor (PU) or pull-down resistor (PD) is a resistor used to ensure a known state for a signal. More specifically, a pull-up resistor or pull-down resistor ensures that a wire will have a high logic lev ...
and the
parasitic capacitance Parasitic capacitance or stray capacitance is the unavoidable and usually unwanted capacitance that exists between the parts of an electronic component or circuit simply because of their proximity to each other. When two electrical conductors a ...
of the bus) and may be additionally delayed by a target's clock stretching. Once SCL is high, the controller waits a minimum time (4 μs for standard-speed I2C) to ensure that the receiver has seen the bit, then pulls it low again. This completes transmission of one bit. After every 8 data bits in one direction, an "acknowledge" bit is transmitted in the other direction. The transmitter and receiver switch roles for one bit, and the original receiver transmits a single "0" bit (ACK) back. If the transmitter sees a "1" bit (NACK) instead, it learns that: * (If controller transmitting to target) The target is unable to accept the data. No such target, command not understood, or unable to accept any more data. * (If target transmitting to controller) The controller wishes the transfer to stop after this data byte. Only the SDA line changes direction during acknowledge bits; the SCL is always controlled by the controller. After the acknowledge bit, the clock line is low and the controller may do one of three things: * Begin transferring another byte of data: the transmitter sets SDA, and the controller pulses SCL high. * Send a "Stop": Set SDA low, let SCL go high, then let SDA go high. This releases the I2C bus. * Send a "Repeated start": Set SDA high, let SCL go high, then pull SDA low again. This starts a new I2C bus message without releasing the bus.


Clock stretching using SCL

One of the more significant features of the I2C protocol is clock stretching. An addressed target device may hold the clock line (SCL) low after receiving (or sending) a byte, indicating that it is not yet ready to process more data. The controller that is communicating with the target may not finish the transmission of the current bit, but must wait until the clock line actually goes high. If the target is clock-stretching, the clock line will still be low (because the connections are open-drain). The same is true if a second, slower, controller tries to drive the clock at the same time. (If there is more than one controller, all but one of them will normally lose arbitration.) The controller must wait until it observes the clock line going high, and an additional minimal time (4 μs for standard I2C) before pulling the clock low again. Although the controller may also hold the SCL line low for as long as it desires (this is not allowed since Rev. 6 of the protocol – subsection 3.1.1), the term "clock stretching" is normally used only when targets do it. Although in theory any clock pulse may be stretched, generally it is the intervals before or after the acknowledgment bit which are used. For example, if the target is a
microcontroller A microcontroller (MC, uC, or μC) or microcontroller unit (MCU) is a small computer on a single integrated circuit. A microcontroller contains one or more CPUs (processor cores) along with memory and programmable input/output peripherals. Pro ...
, its I2C interface could stretch the clock after each byte, until the software decides whether to send a positive acknowledgment or a NACK. Clock stretching is the only time in I2C where the target drives SCL. Many targets do not need to clock stretch and thus treat SCL as strictly an input with no circuitry to drive it. Some controllers, such as those found inside custom ASICs may not support clock stretching; often these devices will be labeled as a "two-wire interface" and not I2C. To maximize bus
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, SMBus places limits on how far clocks may be stretched. Hosts and targets adhering to those limits cannot block access to the bus for more than a short time, which is not a guarantee made by pure I2C systems.


Arbitration using SDA

Every controller monitors the bus for start and stop bits and does not start a message while another controller is keeping the bus busy. However, two controllers may start transmission at about the same time; in this case, arbitration occurs. Target transmit mode can also be arbitrated, when a controller addresses multiple targets, but this is less common. In contrast to protocols (such as
Ethernet Ethernet ( ) is a family of wired computer networking technologies commonly used in local area networks (LAN), metropolitan area networks (MAN) and wide area networks (WAN). It was commercially introduced in 1980 and first standardized in 198 ...
) that use random back-off delays before issuing a retry, I2C has a deterministic arbitration policy. Each transmitter checks the level of the data line (SDA) and compares it with the levels it expects; if they do not match, that transmitter has lost arbitration and drops out of this protocol interaction. If one transmitter sets SDA to 1 (not driving a signal) and a second transmitter sets it to 0 (pull to ground), the result is that the line is low. The first transmitter then observes that the level of the line is different from that expected and concludes that another node is transmitting. The first node to notice such a difference is the one that loses arbitration: it stops driving SDA. If it is a controller, it also stops driving SCL and waits for a STOP; then it may try to reissue its entire message. In the meantime, the other node has not noticed any difference between the expected and actual levels on SDA and therefore continues transmission. It can do so without problems because so far the signal has been exactly as it expected; no other transmitter has disturbed its message. If the two controllers are sending a message to two different targets, the one sending the lower target address always "wins" arbitration in the address stage. Since the two controllers may send messages to the same target address, and addresses sometimes refer to multiple targets, arbitration must sometimes continue into the data stages. Arbitration occurs very rarely, but is necessary for proper multi-controller support. As with clock stretching, not all devices support arbitration. Those that do, generally label themselves as supporting "multi-controller" communication. One case which must be handled carefully in multi-controller I2C implementations is that of the controllers talking to each other. One controller may lose arbitration to an incoming message, and must change its role from controller to target in time to acknowledge its own address. In the extremely rare case that two controllers simultaneously send identical messages, both will regard the communication as successful, but the target will only see one message. For this reason, when a target can be accessed by multiple controllers, every command recognized by the target either must be
idempotent Idempotence (, ) is the property of certain operations in mathematics and computer science whereby they can be applied multiple times without changing the result beyond the initial application. The concept of idempotence arises in a number of pl ...
or must be guaranteed never to be issued by two controllers at the same time. (For example, a command which is issued by only one controller need not be idempotent, nor is it necessary for a specific command to be idempotent when some mutual exclusion mechanism ensures that only one controller can be caused to issue that command at any given time.)


Arbitration in SMBus

While I2C only arbitrates between controllers, SMBus uses arbitration in three additional contexts, where multiple targets respond to the controller, and one gets its message through. * Although conceptually a single-controller bus, a target device that supports the "host notify protocol" acts as a controller to perform the notification. It seizes the bus and writes a 3-byte message to the reserved "SMBus Host" address (0x08), passing its address and two bytes of data. When two targets try to notify the host at the same time, one of them will lose arbitration and need to retry. * An alternative target notification system uses the separate SMBALERT# signal to request attention. In this case, the host performs a 1-byte read from the reserved "SMBus Alert Response Address" (0x0C), which is a kind of broadcast address. All alerting targets respond with a data bytes containing their own address. When the target successfully transmits its own address (winning arbitration against others) it stops raising that interrupt. In both this and the preceding case, arbitration ensures that one target's message will be received, and the others will know they must retry. * SMBus also supports an "address resolution protocol", wherein devices return a 16-byte "Unique Device Identifier" (UDID). Multiple devices may respond; the one with the lowest UDID will win arbitration and be recognized.


Arbitration in PMBus

PMBus version 1.3 extends the SMBus alert response protocol in its "zone read" protocol. Targets may be grouped into "zones", and all targets in a zone may be addressed to respond, with their responses masked (omitting unwanted information), inverted (so wanted information is sent as 0 bits, which win arbitration), or reordered (so the most significant information is sent first). Arbitration ensures that the highest priority response is the one first returned to the controller. PMBus reserves I2C addresses 0x28 and 0x37 for zone reads and writes, respectively.


Differences between modes

There are several possible operating modes for I2C communication. All are compatible in that the ''standard mode'' may always be used, but combining devices of different capabilities on the same bus can cause issues, as follows: * ''Fast mode'' is highly compatible and simply tightens several of the timing parameters to achieve speed. ''Fast mode'' is widely supported by I2C target devices, so a controller may use it as long as it knows that the bus capacitance and pull-up strength allow it. * ''Fast mode plus'' achieves up to using more powerful (20 mA) drivers and pull-ups to achieve faster rise and fall times. Compatibility with ''standard'' and ''fast mode'' devices (with 3 mA pull-down capability) can be achieved if there is some way to reduce the strength of the pull-ups when talking to them. * ''High speed mode'' () is compatible with normal I2C devices on the same bus, but requires the controller have an active pull-up on the clock line which is enabled during high speed transfers. The first data bit is transferred with a normal open-drain rising clock edge, which may be stretched. For the remaining seven data bits, and the ACK, the controller drives the clock high at the appropriate time and the target may not stretch it. All high-speed transfers are preceded by a single-byte "controller code" at fast or standard speed. This code serves three purposes: *# it tells high-speed target devices to change to high-speed timing rules, *# it ensures that fast or normal speed devices will not try to participate in the transfer (because it does not match their address), and *# because it identifies the controller (there are eight controller codes, and each controller must use a different one), it ensures that arbitration is complete before the high-speed portion of the transfer, and so the high-speed portion need not make allowances for that ability. * ''Ultra-Fast mode'' is essentially a write-only I2C subset, which is incompatible with other modes except in that it is easy to add support for it to an existing I2C interface hardware design. Only one controller is permitted, and it actively drives data lines at all times to achieve a transfer rate. Clock stretching, arbitration, read transfers, and acknowledgements are all omitted. It is mainly intended for animated LED displays where a transmission error would only cause an inconsequential brief visual glitch. The resemblance to other I2C bus modes is limited to: ** the start and stop conditions are used to delimit transfers, ** I2C addressing allows multiple target devices to share the bus without SPI bus style target select signals, and ** a ninth clock pulse is sent per byte transmitted marking the position of the unused acknowledgement bits. Some of the vendors provide a so-called non-standard ''Turbo mode'' with a speed up to . In all modes, the clock frequency is controlled by the controller(s), and a longer-than-normal bus may be operated at a slower-than-nominal speed by underclocking.


Circuit interconnections

I2C is popular for interfacing peripheral circuits to prototyping systems, such as the
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and
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. I2C does not employ a standardized connector, however, board designers have created various wiring schemes for I2C interconnections. To minimize the possible damage due to plugging 0.1-inch headers in backwards, some developers have suggested using alternating signal and power connections of the following wiring schemes: (GND, SCL, VCC, SDA) or (VCC, SDA, GND, SCL). The vast majority of applications use I2C in the way it was originally designed—peripheral ICs directly wired to a processor on the same printed circuit board, and therefore over relatively short distances of less than , without a connector. However using a differential driver, an alternate version of I2C can communicate up to 20 meters (possibly over 100 meters) over CAT5 or other cable. Several standard connectors carry I2C signals. For example, the UEXT, the 10-pin iPack, and the
6P6C A modular connector is a type of electrical connector for cords and cables of electronic devices and appliances, such as in computer networking, telecommunication equipment, and audio headsets. Modular connectors were originally developed for ...
Lego Mindstorms NXT connectors carry I2C. Every
HDMI High-Definition Multimedia Interface (HDMI) is a proprietary digital interface used to transmit high-quality video and audio signals between devices. It is commonly used to connect devices such as televisions, computer monitors, projectors, gam ...
and most DVI and VGA connectors carry DDC2 data over I2C. Additionally,
8P8C A modular connector is a type of electrical connector for cords and cables of electronic devices and appliances, such as in computer networking, telecommunication equipment, and audio headsets. Modular connectors were originally developed for ...
connectors and a CAT5 cable normally used for the
Ethernet physical layer The physical-layer specifications of the Ethernet family of computer network standards are published by the Institute of Electrical and Electronics Engineers (IEEE), which defines the electrical or optical properties and the transfer speed of ...
can sometimes be used to carry differential-encoded or boosted single-ended I2C signals.


Buffering and multiplexing

When there are many I2C devices in a system, there can be a need to include bus buffers or
multiplexer In electronics, a multiplexer (or mux; spelled sometimes as multiplexor), also known as a data selector, is a device that selects between several Analog signal, analog or Digital signal (electronics), digital input signals and forwards the sel ...
s to split large bus segments into smaller ones. This can be necessary to keep the capacitance of a bus segment below the allowable value or to allow multiple devices with the same address to be separated by a multiplexer. Many types of multiplexers and buffers exist and all must take into account the fact that I2C lines are specified to be bidirectional. Multiplexers can be implemented with analog switches, which can tie one segment to another. Analog switches maintain the bidirectional nature of the lines but do not isolate the capacitance of one segment from another or provide buffering capability. Buffers can be used to isolate capacitance on one segment from another and/or allow I2C to be sent over longer cables or traces. Buffers for bi-directional lines such as I2C must use one of several schemes for preventing latch-up. I2C is open-drain, so buffers must drive a low on one side when they see a low on the other. One method for preventing latch-up is for a buffer to have carefully selected input and output levels such that the output level of its driver is higher than its input threshold, preventing it from triggering itself. For example, a buffer may have an input threshold of 0.4 V for detecting a low, but an output low level of 0.5 V. This method requires that all other devices on the bus have thresholds which are compatible and often means that multiple buffers implementing this scheme cannot be put in series with one another. Alternatively, other types of buffers exist that implement current amplifiers or keep track of the state (i.e., which side drove the bus low) to prevent latch-up. The state method typically means that an unintended pulse is created during a hand-off when one side is driving the bus low, then the other drives it low, then the first side releases (this is common during an I2C acknowledgement).


Sharing SCL between multiple buses

When having a single controller, it is possible to have multiple I2C buses share the same SCL line. The packets on each bus are either sent one after the other or at the same time. This is possible, because the communication on each bus can be subdivided in alternating short periods with high SCL followed by short periods with low SCL. And the clock can be stretched, if one bus needs more time in one state. Advantages are using targets devices with the same address at the same time and saving connections or a faster throughput by using several data lines at the same time.


Line state table

These tables show the various atomic states and bit operations that may occur during an I2C message.


Addressing structure


7-bit addressing


10-bit addressing


Reserved addresses in 7-bit address space

Two groups of 8 addresses each are reserved for special functions: * From: 0000 000 to 0000 111 * From: 1111 000 to 1111 111 In addition, the remaining 112 addresses are designated for specific classes of device, and some of them are further reserved by either related standards or common usage. SMBus reserves some additional addresses. In particular, 0001 000 is reserved for the SMBus host, which may be used by controller-capable devices, 0001 100 is the "SMBus alert response address" which is polled by the host after an out-of-band interrupt, and 1100 001 is the default address which is initially used by devices capable of dynamic address assignment.


Non-reserved addresses in 7-bit address space

Although MSB 1111 is reserved for Device ID and 10-bit target (slave) addressing, it is also used by VESA DDC display dependent devices such as
pointing device A pointing device is a human interface device that allows a User (computing)#End-user, user to input Three-dimensional space, spatial (i.e., continuous and multi-dimensional) data to a computer. Graphical user interfaces (GUI) and Computer- ...
s.


Transaction format

An I2C ''transaction'' consists of one or more ''messages''. Each message begins with a start symbol, and the transaction ends with a stop symbol. Start symbols after the first, which begin a message but not a transaction, are referred to as ''repeated start'' symbols. Each message is a read or a write. A transaction consisting of a single message is called either a read or a write transaction. A transaction consisting of multiple messages is called a combined transaction. The most common form of the latter is a write message providing intra-device address information, followed by a read message. Many I2C devices do not distinguish between a combined transaction and the same messages sent as separate transactions, but not all. The device ID protocol requires a single transaction; targets are forbidden from responding if they observe a stop symbol. Configuration, calibration or self-test modes which cause the target to respond unusually are also often automatically terminated at the end of a transaction.


Timing diagram

# Data transfer is initiated with a ''start'' condition (S) signalled by SDA being pulled low while SCL stays high. # SCL is pulled low, and SDA sets the first data bit level while keeping SCL low (during blue bar time). # The data is sampled (received) when SCL rises for the first bit (B1). For a bit to be valid, SDA must not change between a rising edge of SCL and the subsequent falling edge (the entire green bar time). # This process repeats, SDA transitioning while SCL is low, and the data being read while SCL is high (B2 through Bn). # The final bit is followed by a clock pulse, during which SDA is pulled low in preparation for the ''stop'' bit. # A ''stop'' condition (P) is signalled when SCL rises, followed by SDA rising. To avoid false marker detection, there is a minimum delay between the SCL falling edge and changing SDA, and between changing SDA and the SCL rising edge. The minimum delay time is dependent upon the data transfer rate in use. Note that an I2C message containing data bits (including acknowledgements) contains clock pulses.


Software Design

I2C lends itself to a "bus driver" software design. Software for attached devices is written to call a "bus driver" that handles the actual low-level I2C hardware. This permits the driver code for attached devices to port easily to other hardware, including a bit-banging design.


Example of bit-banging the I2C protocol

Below is an example of bit-banging the I2C protocol as an I2C controller (master). The example is written in pseudo C. It illustrates all of the I2C features described before (clock stretching, arbitration, start/stop bit, ack/nack). // Hardware-specific support functions that MUST be customized: #define I2CSPEED 100 void I2C_delay(void); bool read_SCL(void); // Return current level of SCL line, 0 or 1 bool read_SDA(void); // Return current level of SDA line, 0 or 1 void set_SCL(void); // Do not drive SCL (set pin high-impedance) void clear_SCL(void); // Actively drive SCL signal low void set_SDA(void); // Do not drive SDA (set pin high-impedance) void clear_SDA(void); // Actively drive SDA signal low void arbitration_lost(void); bool started = false; // global data void i2c_start_cond(void) void i2c_stop_cond(void) // Write a bit to I2C bus void i2c_write_bit(bool bit) // Read a bit from I2C bus bool i2c_read_bit(void) // Write a byte to I2C bus. Return 0 if ack by the target. bool i2c_write_byte(bool send_start, bool send_stop, unsigned char byte) // Read a byte from I2C bus unsigned char i2c_read_byte(bool nack, bool send_stop) void I2C_delay(void)


Operating system support

* In
AmigaOS AmigaOS is a family of proprietary native operating systems of the Amiga and AmigaOne personal computers. It was developed first by Commodore International and introduced with the launch of the first Amiga, the Amiga 1000, in 1985. Early versions ...
one can use the i2c.resource component for AmigaOS 4.x and MorphOS 3.x or the shared library ''i2c.library'' by Wilhelm Noeker for older systems. *
Arduino Arduino () is an Italian open-source hardware and open-source software, software company, project, and user community that designs and manufactures single-board microcontrollers and microcontroller kits for building digital devices. Its hardwar ...
developers can use the "Wire" library. *
CircuitPython CircuitPython is an open-source derivative of the MicroPython programming language targeted toward students and beginners. Development of CircuitPython is supported by Adafruit Industries. It is a software implementation of the programming langua ...
and MicroPython developers can use the busio.I2C or machine.I2C classes respectively. * Maximite supports I2C communications natively as part of its MMBasic. *
PICAXE PICAXE is a microcontroller system based on a range of Microchip Technology, Microchip PIC microcontroller, PIC microcontrollers. PICAXE devices are Microchip PIC devices with pre-programmed firmware that enables bootloading of code directly from a ...
uses the i2c and hi2c commands. * eCos supports I2C for several hardware architectures. * ChibiOS/RT supports I2C for several hardware architectures. *
FreeBSD FreeBSD is a free-software Unix-like operating system descended from the Berkeley Software Distribution (BSD). The first version was released in 1993 developed from 386BSD, one of the first fully functional and free Unix clones on affordable ...
,
NetBSD NetBSD is a free and open-source Unix-like operating system based on the Berkeley Software Distribution (BSD). It was the first open-source BSD descendant officially released after 386BSD was fork (software development), forked. It continues to ...
and
OpenBSD OpenBSD is a security-focused operating system, security-focused, free software, Unix-like operating system based on the Berkeley Software Distribution (BSD). Theo de Raadt created OpenBSD in 1995 by fork (software development), forking NetBSD ...
also provide an I2C framework, with support for a number of common controllers and sensors. ** Since
OpenBSD OpenBSD is a security-focused operating system, security-focused, free software, Unix-like operating system based on the Berkeley Software Distribution (BSD). Theo de Raadt created OpenBSD in 1995 by fork (software development), forking NetBSD ...
3.9 (released ), a central subsystem probes all possible sensor chips at once during boot, using an
ad hoc ''Ad hoc'' is a List of Latin phrases, Latin phrase meaning literally for this. In English language, English, it typically signifies a solution designed for a specific purpose, problem, or task rather than a Generalization, generalized solution ...
weighting scheme and a local caching function for reading register values from the I2C targets; this makes it possible to probe sensors on general-purpose off-the-shelf i386/amd64 hardware during boot without any configuration by the user nor a noticeable probing delay; the matching procedures of the individual drivers then only has to rely on a string-based "friendly-name" for matching; as a result, most I2C sensor drivers are automatically enabled by default in applicable architectures without ill effects on stability; individual sensors, both I2C and otherwise, are exported to the userland through the sysctl hw.sensors framework. , OpenBSD has over two dozen device drivers on I2C that export some kind of a sensor through the hw.sensors framework, and the majority of these drivers are fully enabled by default in i386/amd64 GENERIC kernels of OpenBSD. ** In
NetBSD NetBSD is a free and open-source Unix-like operating system based on the Berkeley Software Distribution (BSD). It was the first open-source BSD descendant officially released after 386BSD was fork (software development), forked. It continues to ...
, over two dozen I2C target devices exist that feature hardware monitoring sensors, which are accessible through the sysmon envsys framework as
property list In the macOS, iOS, NeXTSTEP, and GNUstep programming frameworks, property list files are files that store serialized objects. Property list files use the filename extension .plist, and thus are often referred to as p-list files. Property l ...
s. On general-purpose hardware, each driver has to do its own probing, hence all drivers for the I2C targets are disabled by default in NetBSD in GENERIC i386/amd64 builds. * In
Linux Linux ( ) is a family of open source Unix-like operating systems based on the Linux kernel, an kernel (operating system), operating system kernel first released on September 17, 1991, by Linus Torvalds. Linux is typically package manager, pac ...
, I2C is handled with a device driver for the specific device, and another for the I2C (or SMBus) adapter to which it is connected. Hundreds of such drivers are part of current Linux kernel releases. * In
Mac OS X macOS, previously OS X and originally Mac OS X, is a Unix, Unix-based operating system developed and marketed by Apple Inc., Apple since 2001. It is the current operating system for Apple's Mac (computer), Mac computers. With ...
, there are about two dozen I2C kernel extensions that communicate with sensors for reading voltage, current, temperature, motion, and other physical status. * In
Microsoft Windows Windows is a Product lining, product line of Proprietary software, proprietary graphical user interface, graphical operating systems developed and marketed by Microsoft. It is grouped into families and subfamilies that cater to particular sec ...
, I2C is implemented by the respective device drivers of much of the industry's available hardware. For HID embedded/ SoC devices, Windows 8 and later have an integrated I²C bus driver. * In Windows CE, I2C is implemented by the respective device drivers of much of the industry's available hardware. * Unison OS, a POSIX RTOS for IoT, supports I2C for several MCU and MPU hardware architectures. * In
RISC OS RISC OS () is an operating system designed to run on ARM architecture, ARM computers. Originally designed in 1987 by Acorn Computers of England, it was made for use in its new line of ARM-based Acorn Archimedes, Archimedes personal computers an ...
, I2C is provided with a generic I2C interface from the IO controller and supported from the OS module system * In Sinclair QDOS and
Minerva Minerva (; ; ) is the Roman goddess of wisdom, justice, law, victory, and the sponsor of arts, trade, and strategy. She is also a goddess of warfare, though with a focus on strategic warfare, rather than the violence of gods such as Mars. Be ...
QL
operating systems An operating system (OS) is system software that manages computer hardware and software resources, and provides common daemon (computing), services for computer programs. Time-sharing operating systems scheduler (computing), schedule tasks for ...
I2C is supported by a set of extensions provided by TF Services. * In Zephyr OS, I2C is supported through the i2c device driver API. This API provides a generic interface for communicating with I2C devices, allowing for a wide range of I2C devices to be supported.


Development tools

When developing or troubleshooting systems using I2C, visibility at the level of hardware signals can be important.


Host adapters

There are a number of I2C host adapter hardware solutions for making a I2C controller or target connection to host computers, running
Linux Linux ( ) is a family of open source Unix-like operating systems based on the Linux kernel, an kernel (operating system), operating system kernel first released on September 17, 1991, by Linus Torvalds. Linux is typically package manager, pac ...
, Mac or
Windows Windows is a Product lining, product line of Proprietary software, proprietary graphical user interface, graphical operating systems developed and marketed by Microsoft. It is grouped into families and subfamilies that cater to particular sec ...
. Most options are
USB Universal Serial Bus (USB) is an industry standard, developed by USB Implementers Forum (USB-IF), for digital data transmission and power delivery between many types of electronics. It specifies the architecture, in particular the physical ...
-to-I2C adapters. Not all of them require proprietary drivers or APIs.


Protocol analyzers

I2C protocol analyzers are tools that sample an I2C bus and decode the electrical signals to provide a higher-level view of the data being transmitted on the bus.


Logic analyzers

When developing and/or troubleshooting the I2C bus, examination of hardware signals can be very important. Logic analyzers are tools that collect, analyze, decode, and store signals, so people can view the high-speed waveforms at their leisure. Logic analyzers display time stamps of each signal level change, which can help find protocol problems. Most logic analyzers have the capability to decode bus signals into high-level protocol data and show ASCII data.


Popular cable systems

On various off the shelf modules, there are some main connectors and pinouts: * ''Qwiic'': introduced by Sparkfun in 2017, uses 4-pin JST SH 1.0mm connectors ** pinout: GND, Vcc (3.3V), SDA, SCL * ''STEMMA QT'': introduced by Adafruit in 2018, is not necessarily compatible with Qwiic, due to allowing a wider voltage range (3V–5V); device board size is standardized ** pinout: GND, Vcc (3V–5V), SDA, SCL * ''STEMMA'': by Adafruit, utilizes 4-pin JST PH 2.0mm connectors (3-pin connectors are meant for analog/PWM use) ** pinout: GND, Vcc (3V–5V), SDA, SCL * ''Grove'': by Seeed Studio, utilizes 4-pin 2.0mm proprietary connectors, known as A2005 series, or 1125S-4P ** pinout: GND, Vcc (3.3/5V), SDA, SCL * ''Gravity'': by DFRobot utilizes 4-pin JST PH 2.0mm connectors, same connector as STEMMA but with different pin use ** pinout: SDA, SCL, GND, Vcc (3.3/5V) * ''nodeLynk Interface'': utilizes 4-pin Molex SL 70553 series 2.54mm connectors ** pinout: SCL, SDA, Vcc (5V), GND * ''Breakout Garden'': by Pimoroni utilizes 5-pin 2.54mm edge connector on 1.6mm thick circuitboard; pinout compatible with Raspberry Pi header ** pinout: Vcc (2V to 6V), SDA, SCL, unused/interrupt, GND * '' UEXT'': by Olimex is a 5x2 2.54mm shrouded header connector, implementing together I2C, SPI, and UART * '' Pmod Interface'': by Digilent, a 6-pin single-line 2.54mm header connector, used for I2C, SPI, or UART; often on FPGA boards ** pinout ("type 6", the I2C variant): unused/GPIO/interrupt from slave to master, unused/GPIO/reset, SCL, SDA, GND, Vcc (3.3V)


Limitations

The assignment of target addresses is a weakness of I2C. Seven bits is too few to prevent address collisions between the many thousands of available devices. What alleviates the issue of address collisions between different vendors and also allows to connect to several identical devices is that manufacturers dedicate pins that can be used to set the target address to one of a few address options per device. Two or three pins is typical, and with many devices, there are three or more wiring options per address pin.Linear Technology's LTC4151
has two pins for address selection, each of which can be tied high or low or left unconnected, offering 9 different addresses.
Maxim's MAX7314
has a single pin for address selection to be tied high or low or connected to SDA or SCL, offering 4 different addresses.
TI's UCD9224
uses two ADC channels discriminating twelve levels each to select any valid 7-bit address.
10-bit I2C addresses are not yet widely used, and many host operating systems do not support them. Neither is the complex SMBus "ARP" scheme for dynamically assigning addresses (other than for PCI cards with SMBus presence, for which it is required). Automatic bus configuration is a related issue. A given address may be used by a number of different protocol-incompatible devices in various systems, and hardly any device types can be detected at runtime. For example, 0x51 may be used by a 24LC02 or 24C32 EEPROM, with incompatible addressing; or by a PCF8563 RTC, which cannot reliably be distinguished from either (without changing device state, which might not be allowed). The only reliable configuration mechanisms available to hosts involve out-of-band mechanisms such as tables provided by system firmware, which list the available devices. Again, this issue can partially be addressed by ARP in SMBus systems, especially when vendor and product identifiers are used; but that has not really caught on. The Rev. 3 version of the I2C specification adds a device ID mechanism. I2C supports a limited range of speeds. Hosts supporting the multi-megabit speeds are rare. Support for the Fm+ speed is more widespread, since its electronics are simple variants of what is used at lower speeds. Many devices do not support the speed (in part because SMBus does not yet support it). I2C nodes implemented in software (instead of dedicated hardware) may not even support the speed; so the whole range defined in the specification is rarely usable. All devices must at least partially support the highest speed used or they may spuriously detect their device address. Devices are allowed to stretch clock cycles to suit their particular needs, which can starve bandwidth needed by faster devices and increase latencies when talking to other device addresses. Bus capacitance also places a limit on the transfer speed, especially when current sources are not used to decrease signal rise times. Because I2C is a shared bus, there is the potential for any device to have a fault and hang the entire bus. For example, if any device holds the SDA or SCL line low, it prevents the controller from sending START or STOP commands to reset the bus. Thus it is common for designs to include a reset signal that provides an external method of resetting the bus devices. However many devices do not have a dedicated reset pin, forcing the designer to put in circuitry to allow devices to be power-cycled if they need to be reset. Because of these limits (address management, bus configuration, potential faults, speed), few I2C bus segments have even a dozen devices. Instead, it is common for systems to have several smaller segments. One might be dedicated to use with high-speed devices, for low-latency power management. Another might be used to control a few devices where latency and throughput are not important issues; yet another segment might be used only to read EEPROM chips describing add-on cards (such as the SPD standard used with DRAM sticks). On very low-power systems, the pull-up resistors can use more power than the entire rest of the design combined. On these, the resistors are often powered by a switchable voltage source, such as a DIO from a microcontroller. The pull-ups also limit the speed of the bus and have a small additional cost. Therefore, some designers are turning to other serial buses that do not need pull-ups, such as I3C or SPI.


Derivative technologies

I2C is the basis for the ACCESS.bus, the
VESA VESA (), formally known as Video Electronics Standards Association, is an American standards organization, technical standards organization for computer display standards. The organization was incorporated in California in July 1989To retrieve ...
Display Data Channel (DDC) interface, the System Management Bus (SMBus), Power Management Bus (PMBus) and the Intelligent Platform Management Bus (IPMB, one of the protocols of IPMI). These variants have differences in voltage and clock frequency ranges, and may have interrupt lines. High-availability systems ( AdvancedTCA, MicroTCA) use 2-way redundant I2C for shelf management. Multi-controller I2C capability is a requirement in these systems. TWI (Two-Wire Interface) or TWSI (Two-Wire Serial Interface) is essentially the same bus implemented on various system-on-chip processors from Atmel and other vendors. Vendors use the name TWI, even though I2C is not a registered trademark as of 2014-11-07. Trademark protection only exists for the respective logo (see upper right corner), and patents on I2C have now lapsed. According to Microchip Technology, TWI and I2C have a few differences. One of them is that TWI does not support START byte. In some cases, use of the term "two-wire interface" indicates incomplete implementation of the I2C specification. Not supporting arbitration or clock stretching is one common limitation, which is still useful for a single controller communicating with simple targets that never stretch the clock. MIPI I3C sensor interface standard (I3C) is a development of I2C, under development in 2017.


Revisions


See also

* List of network buses * ACCESS.bus * I3C * Power Management Bus * System Management Bus * UEXT Connector * VESA Display Data Channel


References


Further reading

* (248 pages) * (314 pages)


External links


Official I2C Specification Rev 6 (free)
- NXP
Detailed I2C Introduction & Primer

I2C Pullup Resistor Calculation
- TI
Effects of Varying I2C Pullup Resistors (Scope Captures of 5V I2C with 9 Different Pullup Resistances)
{{DEFAULTSORT:I2c Serial buses