A SHA instruction set is a set of extensions to the
x86
x86 (also known as 80x86 or the 8086 family) is a family of complex instruction set computer (CISC) instruction set architectures initially developed by Intel, based on the 8086 microprocessor and its 8-bit-external-bus variant, the 8088. Th ...
and
ARM
In human anatomy, the arm refers to the upper limb in common usage, although academically the term specifically means the upper arm between the glenohumeral joint (shoulder joint) and the elbow joint. The distal part of the upper limb between ...
instruction set architecture
In computer science, an instruction set architecture (ISA) is an abstract model that generally defines how software controls the CPU in a computer or a family of computers. A device or program that executes instructions described by that ISA, ...
which support
hardware acceleration
Hardware acceleration is the use of computer hardware designed to perform specific functions more efficiently when compared to software running on a general-purpose central processing unit (CPU). Any transformation of data that can be calcula ...
of
Secure Hash Algorithm (SHA) family. It was specified in 2013 by Intel. Instructions for
SHA-512
SHA-2 (Secure Hash Algorithm 2) is a set of cryptographic hash functions designed by the United States National Security Agency (NSA) and first published in 2001. They are built using the Merkle–Damgård construction, from a one-way compression ...
was introduced in
Arrow Lake and
Lunar Lake in 2024.
x86 architecture processors
The original
SSE-based extensions added four instructions supporting
SHA-1
In cryptography, SHA-1 (Secure Hash Algorithm 1) is a hash function which takes an input and produces a 160-bit (20-byte) hash value known as a message digest – typically rendered as 40 hexadecimal digits. It was designed by the United States ...
and three for
SHA-256
SHA-2 (Secure Hash Algorithm 2) is a set of cryptographic hash functions designed by the United States National Security Agency (NSA) and first published in 2001. They are built using the Merkle–Damgård construction, from a one-way compressi ...
.
* SHA-1:
SHA1RNDS4
,
SHA1NEXTE
,
SHA1MSG1
,
SHA1MSG2
* SHA-256:
SHA256RNDS2
,
SHA256MSG1
,
SHA256MSG2
The newer SHA-512 instruction set comprises
AVX-based versions of the original SHA
instruction set
In computer science, an instruction set architecture (ISA) is an abstract model that generally defines how software controls the CPU in a computer or a family of computers. A device or program that executes instructions described by that ISA, s ...
marked with a
V
prefix and these three new AVX-based instructions for
SHA-512
SHA-2 (Secure Hash Algorithm 2) is a set of cryptographic hash functions designed by the United States National Security Agency (NSA) and first published in 2001. They are built using the Merkle–Damgård construction, from a one-way compression ...
:
*
VSHA512RNDS2
,
VSHA512MSG1
,
VSHA512MSG2
AMD
All recent AMD processors support the original SHA instruction set:
* AMD
Zen
Zen (; from Chinese: ''Chán''; in Korean: ''Sŏn'', and Vietnamese: ''Thiền'') is a Mahayana Buddhist tradition that developed in China during the Tang dynasty by blending Indian Mahayana Buddhism, particularly Yogacara and Madhyamaka phil ...
(2017) and later processors.
Intel
The following Intel processors support the original SHA instruction set:
* Intel
Goldmont (2016) and later Atom microarchitecture processors.
* Intel
Cannon Lake (2018/2019),
Ice Lake (2019) and later processors for laptops ("mainstream mobile").
* Intel
Rocket Lake
Rocket Lake is Intel's codename for its 11th generation Core microprocessors. Released on March 30, 2021, it is based on the new Cypress Cove microarchitecture, a variant of Sunny Cove (used by Intel's Ice Lake mobile processors) backporte ...
(2021) and later processors for desktop computers.
The following Intel processors will support the newer SHA-512 instruction set:
* Intel
Arrow Lake and
Lunar Lake processors.
References
External links
* Chapter 8 of
AMD
Intel
X86 instructions
X86 architecture
Hardware acceleration
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