The instruction unit (I-unit or IU), also called, e.g., instruction fetch unit (IFU), instruction issue unit (IIU), instruction sequencing unit (ISU), in a
central processing unit
A central processing unit (CPU), also called a central processor, main processor, or just processor, is the primary Processor (computing), processor in a given computer. Its electronic circuitry executes Instruction (computing), instructions ...
(CPU) is responsible for organizing program instructions to be fetched from memory, and executed, in an appropriate order, and for forwarding them to an
execution unit (E-unit or EU). The I-unit may also do, e.g., address resolution, pre-fetching, prior to forwarding an instruction. It is a part of the
control unit
The control unit (CU) is a component of a computer's central processing unit (CPU) that directs the operation of the processor. A CU typically uses a binary decoder to convert coded instructions into timing and control signals that direct the op ...
, which in turn is part of the CPU.
In the simplest style of
computer architecture, the
instruction cycle The instruction cycle (also known as the fetch–decode–execute cycle, or simply the fetch–execute cycle) is the cycle that the central processing unit (CPU) follows from boot-up until the computer has shut down in order to process instructions ...
is very rigid, and runs exactly as specified by the
programmer
A programmer, computer programmer or coder is an author of computer source code someone with skill in computer programming.
The professional titles Software development, ''software developer'' and Software engineering, ''software engineer' ...
. In the instruction fetch part of the cycle, the value of the
instruction pointer (IP) register is the address of the next instruction to be fetched. This value is placed on the
address bus
In computer architecture, a bus (historically also called a data highway or databus) is a communication system that transfers data between components inside a computer or between computers. It encompasses both hardware (e.g., wires, optical ...
and sent to the
memory unit; the memory unit returns the instruction at that address, and it is latched into the
instruction register
In computing, the instruction register (IR) or current instruction register (CIR) is the part of a CPU's control unit that holds the instruction currently being executed or decoded. In simple processors, each instruction to be executed is loaded ...
(IR); and the value of the IP is incremented or over-written by a new value (in the case of a jump or branch instruction), ready for the next instruction cycle.
This becomes a lot more complicated, though, once performance-enhancing features are added, such as
instruction pipelining,
out-of-order execution
In computer engineering, out-of-order execution (or more formally dynamic execution) is an instruction scheduling paradigm used in high-performance central processing units to make use of instruction cycles that would otherwise be wasted. In t ...
, and even just the introduction of a simple
instruction cache
A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory. A cache is a smaller, faster memory, located closer to a processor core, which ...
.
[ John L. Hennessy and David A. Patterson (1990), ''Computer Architecture: a quantitative approach'', Morgan Kaufmann Publishers, Palo Alto, USA, ]
See also
*
Branch prediction
In computer architecture, a branch predictor is a digital circuit that tries to guess which way a branch (e.g., an if–then–else structure) will go before this is known definitively. The purpose of the branch predictor is to improve the flow ...
and the branch prediction buffer
**
Branch target predictor and the branch target buffer
**
Branch delay slot
In computer architecture, a delay slot is an instruction slot being executed without the effects of a preceding instruction. The most common form is a single arbitrary instruction located immediately after a branch instruction on a RISC or DS ...
*
Instruction scheduling
**
Instruction selection __NOTOC__
In computer science, ''instruction selection'' is the stage of a compiler backend that transforms its middle-level intermediate representation (IR) into a low-level IR. In a typical compiler, instruction selection precedes both instructio ...
**
Data dependency
A data dependency in computer science is a situation in which a program statement (instruction) refers to the data of a preceding statement. In compiler theory, the technique used to discover data dependencies among statements (or instructions) i ...
or
data hazard
**
Scoreboarding
*
Very long instruction word (VLIW)
*
Superscalar
A superscalar processor (or multiple-issue processor) is a CPU that implements a form of parallelism called instruction-level parallelism within a single processor. In contrast to a scalar processor, which can execute at most one single in ...
processor
*
Opcode
In computing, an opcode (abbreviated from operation code) is an enumerated value that specifies the operation to be performed. Opcodes are employed in hardware devices such as arithmetic logic units (ALUs), central processing units (CPUs), and ...
*Analysis of Instruction parallelism, Instruction frequencies, Instruction mix
**
Instruction path length
In computer performance, the instruction path length is the number of machine code instructions required to execute a section of a computer program. The total path length for the entire program could be deemed a measure of the algorithm's perfor ...
or Instruction count
References
Central processing unit
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