Chronologic Simulation was a company based in

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which provided

Verilog Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits, with the highest level of abstraction being at the re ...

HDL simulation products. Chronologic Simulation's main product was the Verilog Compiled Simulator (VCS) HDL simulator. In 1994 Chronologic was sold to Viewlogic Systems and in 1997 Viewlogic was acquired by Synopsys, Inc.

History

In the late 1980s and early 1990s integrated circuits were being designed and verified in Verilog HDL simulators. These simulators were focused on gate level speed and were implemented as language interpreters. Verilog HDL was proprietary and owned by

Cadence Design Systems Cadence Design Systems, Inc. (stylized as cādence)Investor's Business DailCEO Lip-Bu Tan Molds Troubled Cadence Into Long-Term LeaderRetrieved November 12, 2020 is an American multinational corporation, multinational technology and computational ...

after their acquisition in1989 of

Gateway Design Automation "Verilog HDL originated at Automated Integrated Design Systems (later renamed as Gateway Design Automation) in 1985. The company was privately held at that time by Dr. Prabhu Goel, the inventor of the PODEM (Path-Oriented Decision Making) test ...

, the developers of Verilog. There was competition to Verilog from the US DoD

VHDL VHDL (Very High Speed Integrated Circuit Program, VHSIC Hardware Description Language) is a hardware description language that can model the behavior and structure of Digital electronics, digital systems at multiple levels of abstraction, ran ...

language that became an

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standard and in 1991 Cadence made the proprietary Verilog HDL public and created Open Verilog International (OVI) (later renamed Accellera) to standardize it. The founders of Chronologic saw the opening up of Verilog as an opportunity to adopt software compiler techniques and create a fast compiled code Verilog simulator.

Founding team

*John Sanguinetti, CEO and founder *Peter Eichenberger, CTO and founder *Michael McNamara, VP Engineering *Martin Harding, VP Sales *Simon Davidmann, VP Europe

Development

The development of the Verilog Compiled Simulator (VCS) started in 1991 with early development by Sanguinetti, Eichenberger, and McNamara and by 1993 the first version was released, Harding and Davidmann started up the sales channel, and VCS was in use with commercial users and in education and research. VCS initially parsed the Verilog source and using software compiler techniques created C code which is then subsequently compiled into executable binaries to run on the native host computer. The performance of existing Verilog simulators was excellent at the gate level but lacked needed speed at the RTL level. Chronologic's VCS focused on RTL speed and by using cycle based and complier optimization techniques was often reported as being 10-40 times faster than other commercial products.

Acquisition

Chronologic Simulation was acquired in 1994 for $26.5 million by Viewlogic Systems, Inc. though there were complications that resulted in lawsuits that were ultimately resolved in 1995. In 1997 Synopsys, Inc., acquired Viewlogic for $497 million.

Status

VCS is still widely used and has been kept up to date with the evolution in the Verilog language, including features from Superlog that became part of SystemVerilog around 2005. VCS is still a part of Synopsys verification solutions.

References

{{reflist Electronic design automation Hardware description languages