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C-slow retiming is a technique used in conjunction with retiming to improve
throughput Network throughput (or just throughput, when in context) refers to the rate of message delivery over a communication channel, such as Ethernet or packet radio, in a communication network. The data that these messages contain may be delivered ov ...
of a
digital circuit In theoretical computer science, a circuit is a model of computation in which input values proceed through a sequence of gates, each of which computes a function. Circuits of this kind provide a generalization of Boolean circuits and a mathematica ...
. Each
register Register or registration may refer to: Arts entertainment, and media Music * Register (music), the relative "height" or range of a note, melody, part, instrument, etc. * ''Register'', a 2017 album by Travis Miller * Registration (organ), the ...
in a circuit is replaced by a set of ''C'' registers (in series). This creates a circuit with ''C'' independent threads, as if the new circuit contained ''C'' copies of the original circuit. A single computation of the original circuit takes ''C'' times as many
clock cycle In electronics and especially synchronous digital circuits, a clock signal (historically also known as ''logic beat'') oscillates between a high and a low state and is used like a metronome to coordinate actions of digital circuits. A clock signa ...
s to compute in the new circuit. C-slowing by itself increases latency, but
throughput Network throughput (or just throughput, when in context) refers to the rate of message delivery over a communication channel, such as Ethernet or packet radio, in a communication network. The data that these messages contain may be delivered ov ...
remains the same. Increasing the number of registers allows optimization of the circuit through
retiming Retiming is the technique of moving the structural location of latches or registers in a digital circuit to improve its performance, area, and/or power characteristics in such a way that preserves its functional behavior at its outputs. Retiming ...
to reduce the clock period of the circuit. In the best case, the clock period can be reduced by a factor of ''C''. Reducing the clock period of the circuit reduces latency and increases throughput. Thus, for computations that can be multi-threaded, combining C-slowing with retiming can increase the throughput of the circuit, with little, or in the best case, no increase in latency. Since registers are relatively plentiful in
FPGA A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturinghence the term ''Field-programmability, field-programmable''. The FPGA configuration is generally specifi ...
s, this technique is typically applied to circuits implemented with FPGAs.


See also

*
Pipelining Pipelining may refer to: * Pipeline (computing), aka a data pipeline, a set of data processing elements connected in series ** HTTP pipelining, a technique in which multiple HTTP requests are sent on a single TCP connection ** Instruction pipeli ...
*
Barrel processor A barrel processor is a CPU that switches between threads of execution on every cycle. This CPU design technique is also known as "interleaved" or "fine-grained" temporal multithreading. Unlike simultaneous multithreading in modern superscalar arch ...


Resources


PipeRoute: A Pipelining-Aware Router for Reconfigurable ArchitecturesSimple Symmetric Multithreading in Xilinx FPGAsPost Placement C-Slow Retiming for Xilinx Virtex
(.ppt)
Post Placement C-Slow Retiming for Xilinx Virtex
(.pdf)
Exploration of RaPiD-style Pipelined FPGA InterconnectsTime and Area Efficient Pattern Matching on FPGAs
Gate arrays {{Comp-sci-stub