Analog verification is a methodology for performing functional verification on

analog Analog or analogue may refer to: Computing and electronics * Analog signal, in which information is encoded in a continuous variable ** Analog device, an apparatus that operates on analog signals *** Analog electronics, circuits which use analo ...

mixed-signal A mixed-signal integrated circuit is any integrated circuit that has both analog circuits and digital circuits on a single semiconductor die.integrated circuits An integrated circuit or monolithic integrated circuit (also referred to as an IC, a chip, or a microchip) is a set of electronic circuits on one small flat piece (or "chip") of semiconductor material, usually silicon. Transistor count, Large ...

and systems on chip.Henry Chang and Ken Kundert
Verification of Complex Analog and RF IC Designs
''Proceedings of the IEEE'', February 2007. Discussion of analog verification began in 2005 when it started to become recognized that the analog portion of large mixed-signal chips had become so complex that a significant and ever increasing number of these chips were being designed with functional errors in the analog portion that prevented them from operating correctly.

Technical details

Analog verification is built on the idea that transistor level simulation will always be too slow to provide adequate functional verification. Instead, it is necessary to build simple and efficient models of the blocks that make up the analog portion of the design and use those to verify the design. Those models are typically written in

Verilog Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction. It is a ...

Verilog-AMS Verilog-AMS is a derivative of the Verilog hardware description language that includes analog and mixed-signal extensions (AMS) in order to define the behavior of analog and mixed-signal systems. It extends the event-based simulator loops of Veril ...

, but could also be written in

VHDL The VHSIC Hardware Description Language (VHDL) is a hardware description language (HDL) that can model the behavior and structure of digital systems at multiple levels of abstraction, ranging from the system level down to that of logic gat ...

VHDL-AMS VHDL-AMS is a derivative of the hardware description language VHDL (IEEE standard 1076-1993). It includes analog and mixed-signal extensions (AMS) in order to define the behavior of analog and mixed-signal systems (IEEE 1076.1-1999). The VHDL-AMS ...

. However, simply using a simple functional model is not sufficient. It is also necessary to build a comprehensive self-checking testbench, that thoroughly exercises the design and compare its response against a previously written specification for the design. Furthermore, this testbench should be applied in turn to both the model and the design. In this case, the design is represented with a transistor-level schematic. If both the model and the design pass all tests, and if the testbench is comprehensive, then this confirms that the model is consistent with the design and that the design is consistent with the specification. Applying a comprehensive testbench to an entire analog functional unit such as an audio

codec A codec is a device or computer program that encodes or decodes a data stream or signal. ''Codec'' is a portmanteau of coder/decoder. In electronic communications, an endec is a device that acts as both an encoder and a decoder on a signal or ...

power Management IC Power management integrated circuits (power management ICs or PMICs or PMU as unit) are integrated circuits for power management. Although PMIC refers to a wide range of chips (or modules in system-on-a-chip devices), most include several DC/DC ...

, Power Management Unit, serdes, or RF transceiver, represented at the transistor level, is impractical. So instead, the verification proceeds hierarchically. One first builds simple models and testbenches for individual blocks. The block-level testbenches are used to confirm that models match the implementation of the blocks and that the implementation matches the block-level specification. Then testbenches are built for the entire analog functional unit, and applied to the top-level schematic of that unit with the blocks represented with their now verified models. To further improve the tests, one can perform mixed-level simulation, where the testbench for the functional unit is applied with one or two blocks at the transistor level, and all others at the model level.

References

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External links

Verification of Complex Analog and RF IC Designs
Hardware testing IEEE DASC standards