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Perf (Linux)
perf (sometimes called perf_events or perf tools, originally Performance Counters for Linux, PCL) is a performance analyzing tool in Linux, available from Linux kernel version 2.6.31 in 2009. Userspace controlling utility, named perf, is accessed from the command line and provides a number of subcommands; it is capable of statistical profiling of the entire system (both kernel and userland code). It supports hardware performance counters, tracepoints, software performance counters (e.g. hrtimer), and dynamic probes (for example, kprobes or uprobes). In 2012, two IBM engineers recognized perf (along with OProfile) as one of the two most commonly used performance counter profiling tools on Linux. Implementation The interface between the perf utility and the kernel consists of only one syscall and is done via a file descriptor and a mapped memory region.Roberto A. Vitillo ( LBNL)PERFORMANCE TOOLS DEVELOPMENTS 16 June 2011, presentation from "Future computing in particle ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Linux Kernel
The Linux kernel is a Free and open-source software, free and open source Unix-like kernel (operating system), kernel that is used in many computer systems worldwide. The kernel was created by Linus Torvalds in 1991 and was soon adopted as the kernel for the GNU operating system (OS) which was created to be a free software, free replacement for Unix. Since the late 1990s, it has been included in many Linux distributions, operating system distributions, many of which are called Linux. One such Linux kernel operating system is Android (operating system), Android which is used in many mobile and embedded devices. Most of the kernel code is written in C (programming language), C as supported by the GNU compiler collection (GCC) which has extensions beyond standard C. The code also contains assembly language, assembly code for architecture-specific logic such as optimizing memory use and task execution. The kernel has a Modular programming, modular design such that modules can be inte ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Oprofile
In computing, OProfile is a system-wide statistical profiling tool for Linux. John Levon wrote it in 2001 for Linux kernel version 2.4 after his M.Sc. project; it consists of a kernel module, a user-space daemon and several user-space tools. Details OProfile can profile an entire system or its parts, from interrupt routines or drivers, to user-space processes. It has low overhead. The most widely supported kernel mode of uses a system timer (See: Gathering profiling events). However, this mode is unable to measure kernel functions where interrupts are disabled. Newer CPU models support a hardware performance counter mode which uses hardware logic to record events without any active code needed. In Linux 2.2/2.4 only 32-bit x86 and IA64 are supported; in Linux 2.6 there is wider support: x86 (32 and 64 bit), DEC Alpha, MIPS, ARM, sparc64, ppc64, AVR32. Call graphs are supported only on x86 and ARM. In 2012 two IBM engineers recognized OProfile as one of the two most c ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Pentium 4
Pentium 4 is a series of single-core central processing unit, CPUs for Desktop computer, desktops, laptops and entry-level Server (computing), servers manufactured by Intel. The processors were shipped from November 20, 2000 until August 8, 2008. All Pentium 4 CPUs are based on the NetBurst microarchitecture, the successor to the P6 (microarchitecture), P6. The Pentium 4 #Willamette, Willamette (180 nm) introduced SSE2, while the #Prescott, Prescott (90 nm) introduced SSE3 and later 64-bit technology. Later versions introduced Hyper-threading, Hyper-Threading Technology (HTT). The first Pentium 4-branded processor to implement x86-64, 64-bit was the Prescott (90 nm) (February 2004), but this feature was not enabled. Intel subsequently began selling 64-bit Pentium 4s using the ''"E0" revision'' of the Prescotts, being sold on the OEM market as the Pentium 4, model F. The E0 revision also adds eXecute Disable (XD) (Intel's name for the NX bit) to Intel 64. Int ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Intel
Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California, and Delaware General Corporation Law, incorporated in Delaware. Intel designs, manufactures, and sells computer components such as central processing units (CPUs) and related products for business and consumer markets. It is one of the world's List of largest semiconductor chip manufacturers, largest semiconductor chip manufacturers by revenue, and ranked in the Fortune 500, ''Fortune'' 500 list of the List of largest companies in the United States by revenue, largest United States corporations by revenue for nearly a decade, from 2007 to 2016 Fiscal year, fiscal years, until it was removed from the ranking in 2018. In 2020, it was reinstated and ranked 45th, being the List of Fortune 500 computer software and information companies, 7th-largest technology company in the ranking. It was one of the first companies listed on Nasdaq. Intel supplies List of I ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Branch Trace
Branch trace is a computer program debugging tool or analysis technique. It is an abbreviated instruction trace in which only the successful Branch (computer science), branch instructions are recorded. On IBM System/360 this was implemented as part of Program-Event Recording (PER) but was seldom used at the application programming level. Program Event Recording hardware was used and due to the overhead of this tool, it was removed from customer-available MVS systems. Branch tracing is also available for Pentium 4, Xeon and later List of Intel processors, Intel processors. There are dedicated processor commands to enable branch tracing and save executed branches into special Intel Branch Trace Store (BTS) area of resident memory. The Branch Trace Store can be also configured to be a circular buffer, so that last executed branches are recorded. Branch tracing on Intel processors using the Branch Trace Store can cause 40x application run-time slow down. For the Intel Core M and the 5th ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SuperH
SuperH (or SH) is a 32-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Hitachi and currently produced by Renesas. It is implemented by microcontrollers and microprocessors for embedded systems. At the time of introduction, SuperH was notable for having fixed-length 16-bit instructions in spite of its 32-bit architecture. Using smaller instructions had consequences: the processor register, register file was smaller and instructions were generally two-operand format. However for the market the SuperH was aimed at, this was a small price to pay for the improved memory and processor cache efficiency. Later versions of the design, starting with SH-5, included both 16- and 32-bit instructions, with the 16-bit versions mapping onto the 32-bit version inside the CPU. This allowed the machine code to continue using the shorter instructions to save memory, while not demanding the amount of instruction decoding logic needed if they were completely ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
DEC Alpha
Alpha (original name Alpha AXP) is a 64-bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by Digital Equipment Corporation (DEC). Alpha was designed to replace 32-bit VAX complex instruction set computers (CISC) and to be a highly competitive RISC processor for Unix workstations and similar markets. Alpha was implemented in a series of microprocessors originally developed and fabricated by DEC. These microprocessors were most prominently used in a variety of DEC workstations and servers, which eventually formed the basis for almost all of their mid-to-upper-scale lineup. Several third-party vendors also produced Alpha systems, including PC form factor motherboards. Operating systems that support Alpha included OpenVMS (formerly named OpenVMS AXP), Tru64 UNIX (formerly named DEC OSF/1 AXP and Digital UNIX), Windows NT (discontinued after NT 4.0; and prerelease Windows 2000 RC2), Linux (Debian, SUSE, Gentoo and Red Hat), BSD UNIX (NetBS ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Cortex-A9
The ARM Cortex-A9 MPCore is a 32-bit multi-core processor that provides up to 4 cache-coherent cores, each implementing the ARM v7 architecture instruction set. It was introduced in 2007. Features Key features of the Cortex-A9 core are: * out-of-order execution, Out-of-order speculative execution, speculative issue superscalar execution 8-stage instruction pipeline, pipeline giving 8.50 Dhrystone, DMIPS/MHz/core. * ARM NEON, NEON SIMD instruction set extension performing up to 16 operations per instruction (optional). * High performance VFPv3 floating point unit doubling the performance of previous ARM FPUs (optional). * Thumb-2 instruction set encoding reduces the size of programs with little impact on performance. * TrustZone security extensions. * Jazelle DBX support for Java execution. * Jazelle RCT for JIT compilation. * Program Trace Macrocell and CoreSight Design Kit for non-intrusive tracing of instruction execution. * L2 cache controller (0–4 MB). * Multi- ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Cortex-A8
The ARM Cortex-A8 is a 32-bit processor core licensed by ARM Holdings implementing the ARMv7-A architecture. Compared to the ARM11, the Cortex-A8 is a dual-issue superscalar design, achieving roughly twice the instructions per cycle. The Cortex-A8 was the first Cortex design to be adopted on a large scale in consumer devices. Features Key features of the Cortex-A8 core are: * Frequency from 600 MHz to 1 GHz and above * Superscalar dual-issue microarchitecture * NEON SIMD instruction set extension * 13-stage integer pipeline and 10-stage NEON pipeline * VFPv3 floating-point unit * Thumb-2 instruction set encoding * Jazelle RCT (also known as ThumbEE instruction set) * Advanced branch prediction unit with >95% accuracy * Integrated level 2 Cache (0–4 MiB) * 2.0 DMIPS/MHz Chips Several system-on-chips (SoC) have implemented the Cortex-A8 core, including: * Allwinner A1X * Apple A4 * Freescale Semiconductor i.MX51 * Rockchip RK2918, RK2906 * Samsung Exynos ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
ARM Architecture
ARM (stylised in lowercase as arm, formerly an acronym for Advanced RISC Machines and originally Acorn RISC Machine) is a family of reduced instruction set computer, RISC instruction set architectures (ISAs) for central processing unit, computer processors. Arm Holdings develops the ISAs and licenses them to other companies, who build the physical devices that use the instruction set. It also designs and licenses semiconductor intellectual property core, cores that implement these ISAs. Due to their low costs, low power consumption, and low heat generation, ARM processors are useful for light, portable, battery-powered devices, including smartphones, laptops, and tablet computers, as well as embedded systems. However, ARM processors are also used for desktop computer, desktops and server (computing), servers, including Fugaku (supercomputer), Fugaku, the world's fastest supercomputer from 2020 to 2022. With over 230 billion ARM chips produced, , ARM is the most widely used ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
UltraSPARC IV
The UltraSPARC IV ''Jaguar'' and follow-up UltraSPARC IV+ ''Panther'' are microprocessors designed by Sun Microsystems and manufactured by Texas Instruments. They are the fourth generation of UltraSPARC microprocessors, and implement the 64-bit SPARC, SPARC V9 instruction set architecture (ISA). The UltraSPARC IV was originally to be succeeded by the UltraSPARC V ''Millennium'', which was canceled after the announcement of the ''Niagara'', now UltraSPARC T1 microprocessor in early 2004. It was instead succeeded by the Fujitsu-designed SPARC64 VI. The UltraSPARC IV was developed as part of Sun's Throughput Computing initiative, which included the UltraSPARC V ''Millennium'', ''Gemini'' and UltraSPARC T1 ''Niagara'' microprocessors. Of the four original designs in the initiative, two reached production: the UltraSPARC IV and the UltraSPARC T1. Whereas the ''Millennium'' and ''Niagara'' implemented Multithreading (computer architecture)#Coarse-grained multithreading, block multithread ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
UltraSPARC III
The UltraSPARC III, code-named "Cheetah", is a microprocessor that implements the SPARC V9 instruction set architecture (ISA) developed by Sun Microsystems and fabricated by Texas Instruments. It was introduced in 2001 and operates at 600 to 900 MHz. It was succeeded by the UltraSPARC IV in 2004. Gary Lauterbach was the chief architect. History When presented at the '97 Microprocessor Forum, the probable introduction date for the UltraSPARC III was 1999, and it would have competed with Digital Equipment Corporation's Alpha 21264 and Intel's Itanium (Merced). This was not to be the case as it was delayed until 2001. Despite being late, it was awarded the Analysts' Choice Award for Best Server/Workstation Processor of 2001 by ''Microprocessor Report'' for its multiprocessing features. Description The UltraSPARC III is an in-order superscalar microprocessor. The UltraSPARC III was designed for shared memory multiprocessing performance, and it has several features that ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
