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HyperSPARC
The hyperSPARC, code-named "Pinnacle", is a microprocessor that implements the SPARC Version 8 instruction set architecture (ISA) developed by Ross Technology for Cypress Semiconductor. The hyperSPARC was introduced in 1993, and competed with the Sun Microsystems SuperSPARC. Raju Vegesna was the microarchitect. The hyperSPARC was Sun Microsystem's primary competitor in the mid-1990s. When Fujitsu acquired Ross from Cypress, the hyperSPARC was considered to be more important by its new owner than the SPARC64 developed by HAL Computer Systems, also a Fujitsu subsidiary, a view which was shared with analysts. Description The hyperSPARC was a two-way superscalar microprocessor. It had four execution units: an integer unit, a floating-point unit, a load/store unit and a branch unit. The hyperSPARC has an on-die 8 KB instruction cache, from which two instructions were fetched per cycle and decoded. The decoder could not decode new instructions if the previously decoded instruction ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Ross Technology
Ross Technology, Inc. was a semiconductor design and manufacturing company, specializing in SPARC microprocessors. It was founded in Austin, Texas in August 1988 by Dr. Roger D. Ross, a leading computer scientist who headed Motorola's Advanced Microprocessor Division and directed the developments of Motorola's MC68030 and RISC-based 88000 microprocessor families. Dr. Ross was accompanied by Carl Dobbs, Janet Sooch, Steve Goldstein and Travor Smith, who were from Motorola's High-end Microprocessor Division, and were involved in the development of the 88000 microprocessor. He was later was joined by Am29000 engineer Raju Vegesna from AMD, who was originally hired by Dr. Ross at Motorola. Cypress Semiconductor provided initial funding. Original board members included Dr. Ross and well-known figures as Dr. T. J. Rodgers of Cypress Semiconductor, John Doerr of Kleiner Perkins Venture Capital, and L. J. Sevin of Sevin Rosen Venture Capital, who also served as Board Chairma ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SPARC
SPARC (Scalable Processor Architecture) is a reduced instruction set computer (RISC) instruction set architecture originally developed by Sun Microsystems. Its design was strongly influenced by the experimental Berkeley RISC system developed in the early 1980s. First developed in 1986 and released in 1987, SPARC was one of the most successful early commercial RISC systems, and its success led to the introduction of similar RISC designs from many vendors through the 1980s and 1990s. The first implementation of the original 32-bit architecture (SPARC V7) was used in Sun's Sun-4 computer workstation and server systems, replacing their earlier Sun-3 systems based on the Motorola 68000 series of processors. SPARC V8 added a number of improvements that were part of the SuperSPARC series of processors released in 1992. SPARC V9, released in 1993, introduced a 64-bit architecture and was first released in Sun's UltraSPARC processors in 1995. Later, SPARC processors were used in ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SPARC V8
SPARC (Scalable Processor Architecture) is a reduced instruction set computer (RISC) instruction set architecture originally developed by Sun Microsystems. Its design was strongly influenced by the experimental Berkeley RISC system developed in the early 1980s. First developed in 1986 and released in 1987, SPARC was one of the most successful early commercial RISC systems, and its success led to the introduction of similar RISC designs from many vendors through the 1980s and 1990s. The first implementation of the original 32-bit architecture (SPARC V7) was used in Sun's Sun-4 computer workstation and server systems, replacing their earlier Sun-3 systems based on the Motorola 68000 series of processors. SPARC V8 added a number of improvements that were part of the SuperSPARC series of processors released in 1992. SPARC V9, released in 1993, introduced a 64-bit architecture and was first released in Sun's UltraSPARC processors in 1995. Later, SPARC processors were used in symmetri ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
MBus (SPARC)
MBus is a computer bus designed and implemented by Sun Microsystems for communication between high speed computer system components, such as the central processing unit, motherboard and main memory. SBus is used in the same machines to connect add-on cards to the motherboard. MBus was first used in Sun's first multiprocessor SPARC-based system, the SPARCserver 600MP series (launched in 1991), and later found use in the SPARCstation 10 and SPARCstation 20 workstations. The bus permits the integration of several microprocessors on a single motherboard, in a multiprocessing configuration with up to eight CPUs packaged in detachable MBus modules. In practice, the number of processors per MBus is limited to four. Single processor systems were also sold that use the MBus protocol internally, but with the CPUs permanently attached to the motherboard to lower manufacturing costs. MBus specifies a 64-bit datapath, which uses 36-bit physical addressing, giving an address space of 64 ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Register Window
In computer engineering, register windows are a feature which dedicates registers to a subroutine by dynamically aliasing a subset of internal registers to fixed, programmer-visible registers. Register windows are implemented to improve the performance of a processor by reducing the number of stack operations required for function calls and returns. One of the most influential features of the Berkeley RISC design, they were later implemented in instruction set architectures such as AMD Am29000, Intel i960, Sun Microsystems SPARC, and Intel Itanium. General Operation Several sets of registers are provided for the different parts of the program. Registers are deliberately hidden from the programmer to force several subroutines to share processor resources. Rendering the registers invisible can be implemented efficiently; the CPU recognizes the movement from one part of the program to another during a procedure call. It is accomplished by one of a small number of instructions (''pr ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Electronic News
''Electronic News'' was a publication that covered the electronics industry, from semiconductor equipment and materials to military/aerospace electronics to supercomputers. It was originally a weekly trade newspaper, which covered all aspects of the electronics industry, including semiconductors, computers, software, communications, space and even television electronics. History and profile Fairchild Publications started the newspaper in 1957, as a complement to its other trade newspapers, including Women's Wear Daily, Home Furnishing Daily, Supermarket News, among others. At its peak in 1984, ''Electronic News'' took in $25 million in revenue with margins above 50%. The following year, the newspaper began losing advertising and influence to rival '' Electronic Engineering Times'', beginning a decline that eventually led to the newspaper's demise. In 1971, journalist Don Hoefler published a series of articles entitled "Silicon Valley, USA" in ''Electronic News''. This is thought ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Pin Grid Array
A pin grid array (PGA) is a type of integrated circuit packaging. In a PGA, the package is square or rectangular, and the pins are arranged in a regular array on the underside of the package. The pins are commonly spaced 2.54 mm (0.1") apart, and may or may not cover the entire underside of the package. PGAs are often mounted on printed circuit boards using the through hole method or inserted into a socket. PGAs allow for more pins per integrated circuit than older packages, such as dual in-line package (DIP). PGA variants Plastic Plastic pin grid array (PPGA) packaging was used by Intel for late-model Mendocino core Celeron processors based on Socket 370. Some pre-Socket 8 processors also used a similar form factor, although they were not officially referred to as PPGA. Flip chip A flip-chip pin grid array (FC-PGA or FCPGA) is a form of pin grid array in which the die faces downwards on the top of the substrate with the back of the die exposed. This ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Multi-chip Module
A multi-chip module (MCM) is generically an electronic assembly (such as a package with a number of conductor terminals or "pins") where multiple integrated circuits (ICs or "chips"), semiconductor dies and/or other discrete components are integrated, usually onto a unifying substrate, so that in use it can be treated as if it were a larger IC. Other terms for MCM packaging include "heterogeneous integration" or " hybrid integrated circuit". The advantage of using MCM packaging is it allows a manufacturer to use multiple components for modularity and/or to improve yields over a conventional monolithic IC approach. Overview Multi-chip modules come in a variety of forms depending on the complexity and development philosophies of their designers. These can range from using pre-packaged ICs on a small printed circuit board (PCB) meant to mimic the package footprint of an existing chip package to fully custom chip packages integrating many chip dies on a high density interconnection ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Fujitsu
is a Japanese multinational information and communications technology equipment and services corporation, established in 1935 and headquartered in Tokyo. Fujitsu is the world's sixth-largest IT services provider by annual revenue, and the largest in Japan, in 2021. The hardware offerings from Fujitsu are mainly of personal and enterprise computing products, including x86, SPARC and mainframe compatible server products, although the corporation and its subsidiaries also offer a diversity of products and services in the areas of data storage, telecommunications, advanced microelectronics, and air conditioning. It has approximately 126,400 employees and its products and services are available in approximately 180 countries. Fujitsu is listed on the Tokyo Stock Exchange and Nagoya Stock Exchange; its Tokyo listing is a constituent of the Nikkei 225 and TOPIX 100 indices. History 1935 to 2000 Fujitsu was established on June 20, 1935, which makes it one of the oldest ope ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Complementary Metal–oxide–semiconductor
Complementary metal–oxide–semiconductor (CMOS, pronounced "sea-moss", ) is a type of MOSFET, metal–oxide–semiconductor field-effect transistor (MOSFET) semiconductor device fabrication, fabrication process that uses complementary and symmetrical pairs of p-type semiconductor, p-type and n-type semiconductor, n-type MOSFETs for logic functions. CMOS technology is used for constructing integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips (including Nonvolatile BIOS memory, CMOS BIOS), and other digital logic circuits. CMOS technology is also used for analog circuits such as image sensors (CMOS sensors), data conversion, data converters, RF circuits (RF CMOS), and highly integrated transceivers for many types of communication. The CMOS process was originally conceived by Frank Wanlass at Fairchild Semiconductor and presented by Wanlass and Chih-Tang Sah at the International Solid-State Circuits Conference in 1963. Wanlass later filed s:Unit ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Multiprocessing
Multiprocessing is the use of two or more central processing units (CPUs) within a single computer system. The term also refers to the ability of a system to support more than one processor or the ability to allocate tasks between them. There are many variations on this basic theme, and the definition of multiprocessing can vary with context, mostly as a function of how CPUs are defined ( multiple cores on one die, multiple dies in one package, multiple packages in one system unit, etc.). According to some on-line dictionaries, a multiprocessor is a computer system having two or more processing units (multiple processors) each sharing main memory and peripherals, in order to simultaneously process programs. A 2009 textbook defined multiprocessor system similarly, but noting that the processors may share "some or all of the system’s memory and I/O facilities"; it also gave tightly coupled system as a synonymous term. At the operating system level, ''multiprocessing'' is som ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Instruction Pipeline
In computer engineering, instruction pipelining or ILP is a technique for implementing instruction-level parallelism within a single processor. Pipelining attempts to keep every part of the processor busy with some instruction by dividing incoming instructions into a series of sequential steps (the eponymous " pipeline") performed by different processor units with different parts of instructions processed in parallel. Concept and motivation In a pipelined computer, instructions flow through the central processing unit (CPU) in stages. For example, it might have one stage for each step of the von Neumann cycle: Fetch the instruction, fetch the operands, do the instruction, write the results. A pipelined computer usually has "pipeline registers" after each stage. These store information from the instruction and calculations so that the logic gates of the next stage can do the next step. This arrangement lets the CPU complete an instruction on each clock cycle. It is common f ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
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