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Die Shrink
The term die shrink (sometimes optical shrink or process shrink) refers to the List of semiconductor scale examples, scaling of metal–oxide–semiconductor (MOS) devices. The act of shrinking a Die (integrated circuit), die creates a somewhat identical circuit using a more advanced fabrication process, usually involving an advance of lithographic semiconductor node, nodes. This reduces overall costs for a chip company, as the absence of major architectural changes to the Central processing unit, processor lowers research and development costs while at the same time allowing more processor dies to be manufactured on the same piece of silicon wafer, resulting in less cost per product sold. Die shrinks are the key to lower prices and higher performance at Semiconductor company, semiconductor companies such as Samsung Electronics, Samsung, Intel, TSMC, and SK Hynix, and fabless manufacturers such as Advanced Micro Devices, AMD (including the former ATI Technologies, ATI), Nvidia, ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Fabrication Process
Semiconductor device fabrication is the process used to manufacture semiconductor devices, typically integrated circuits (ICs) such as microprocessors, microcontrollers, and memories (such as Random-access memory, RAM and flash memory). It is a multiple-step Photolithography, photolithographic and physico-chemical process (with steps such as thermal oxidation, thin-film deposition, ion-implantation, etching) during which electronic circuits are gradually created on a wafer (electronics), wafer, typically made of pure single-crystal semiconducting material. Silicon is almost always used, but various compound semiconductors are used for specialized applications. This article focuses on the manufacture of integrated circuits, however steps such as etching and photolithography can be used to manufacture other devices such as LCD and OLED displays. The fabrication process is performed in highly specialized semiconductor fabrication plants, also called foundries or "fabs", with the cen ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Semiconductor Node
Semiconductor device fabrication is the process used to manufacture semiconductor devices, typically integrated circuits (ICs) such as microprocessors, microcontrollers, and memories (such as RAM and flash memory). It is a multiple-step photolithographic and physico-chemical process (with steps such as thermal oxidation, thin-film deposition, ion-implantation, etching) during which electronic circuits are gradually created on a wafer, typically made of pure single-crystal semiconducting material. Silicon is almost always used, but various compound semiconductors are used for specialized applications. This article focuses on the manufacture of integrated circuits, however steps such as etching and photolithography can be used to manufacture other devices such as LCD and OLED displays. The fabrication process is performed in highly specialized semiconductor fabrication plants, also called foundries or "fabs", with the central part being the " clean room". In more advanced ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
List Of Semiconductor Scale Examples
Listed are many semiconductor scale examples for various metal–oxide–semiconductor field-effect transistor (MOSFET, or MOS transistor) semiconductor manufacturing process nodes. Timeline of MOSFET demonstrations PMOS and NMOS CMOS (single-gate) Multi-gate MOSFET (MuGFET) Other types of MOSFET Commercial products using micro-scale MOSFETs Products featuring 20 μm manufacturing process * RCA's CD4000 series of integrated circuits (ICs) beginning in 1968. Products featuring 10 μm manufacturing process * Intel 4004, the first single-chip microprocessor CPU, launched in 1971. * Intel 8008 CPU launched in 1972. Products featuring 8 μm manufacturing process * Intel 1103, an early dynamic random-access memory (DRAM) chip launched in 1970. * MOS Technology 6502 1 MHz CPU launched in 1975. Products featuring 6 μm manufacturing process * Toshiba TLCS-12, a microprocessor developed for the Ford EEC (Electronic Engine Co ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
PlayStation 2
The PlayStation 2 (PS2) is a home video game console developed and marketed by Sony Interactive Entertainment, Sony Computer Entertainment. It was first released in Japan on 4 March 2000, in North America on 26 October, in Europe on 24 November, in Australia on 30 November, and other regions thereafter. It is the successor to the PlayStation (console), original PlayStation, as well as the second instalment in the PlayStation brand of consoles. As a sixth generation of video game consoles, sixth-generation console, it competed with Nintendo's GameCube, Sega's Dreamcast, and Microsoft's Xbox (console), Xbox. Announced in 1999, Sony began developing the console after the immense success of its predecessor. In addition to serving as a game console, it features a built-in DVD drive and was priced competitively with standalone DVD players of the time, enhancing its value. Full backward compatibility with original PlayStation games and accessories gave it access to a vast launch libra ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Silicon On Insulator
In semiconductor manufacturing, silicon on insulator (SOI) technology is fabrication of silicon semiconductor devices in a layered silicon–insulator–silicon substrate, to reduce parasitic capacitance within the device, thereby improving performance. SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or sapphire (these types of devices are called silicon on sapphire, or SOS). The choice of insulator depends largely on intended application, with sapphire being used for high-performance radio frequency (RF) and radiation-sensitive applications, and silicon dioxide for diminished short-channel effects in other microelectronics devices. The insulating layer and topmost silicon layer also vary widely with application. Industry need SOI technology is one of several manufacturing strategies to allow the continued miniaturization of microelectronic devices, colloquially referred to ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Athlon 64 X2
The Athlon 64 X2 is the first native dual-core desktop central processing unit (CPU) designed by Advanced Micro Devices (AMD). It was designed from scratch as native dual-core by using an already multi-CPU enabled Athlon 64, joining it with another functional core on one die, and connecting both via a shared dual-channel memory controller/north bridge and additional control logic. The initial versions are based on the E stepping model of the Athlon 64 and, depending on the model, have either 512 or 1024 KB of L2 cache per core. The Athlon 64 X2 can decode instructions for Streaming SIMD Extensions 3 (SSE3), except those few specific to Intel's architecture. The first Athlon 64 X2 CPUs were released in May 2005, in the same month as Intel's first dual-core processor, the Pentium D. In June 2007, AMD released low-voltage variants of their low-end 65 nm Athlon 64 X2, named " Athlon X2". The Athlon X2 processors feature reduced thermal design power (TDP) of 45 Watt (W). The ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
45 nm
Per the International Technology Roadmap for Semiconductors, the 45 nm process is a MOSFET technology node referring to the average half-pitch of a memory cell manufactured at around the 2007–2008 time frame. Matsushita and Intel started mass-producing 45 nm chips in late 2007, and AMD started production of 45 nm chips in late 2008, while IBM, Infineon, Samsung, and Chartered Semiconductor have already completed a common 45 nm process platform. At the end of 2008, SMIC was the first China-based semiconductor company to move to 45 nm, having licensed the bulk 45 nm process from IBM. In 2008, TSMC moved on to a 40nm process. Many critical feature sizes are smaller than the wavelength of light used for lithography (i.e., 193 nm and 248 nm). A variety of techniques, such as larger lenses, are used to make sub-wavelength features. Double patterning has also been introduced to assist in shrinking distances between features, especially if dry lith ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Penryn (microarchitecture)
In Intel's Tick-Tock cycle, the 2007/2008 "Tick" was the shrink of the Core microarchitecture to 45 nanometers as CPUID model 23. In Core 2 processors, it is used with the code names Penryn (Socket P), Wolfdale (LGA 775) and Yorkfield (MCM, LGA 775), some of which are also sold as Celeron, Pentium and Xeon processors. In the Xeon brand, the Wolfdale-DP and Harpertown code names are used for LGA 771 based MCMs with two or four active Wolfdale cores. Architectural improvements over 65-nanometer Core 2 CPUs include a new divider with reduced latency, a new shuffle engine, and SSE4.1 instructions (some of which are enabled by the new single-cycle shuffle engine). Maximum L2 cache size per chip was increased from 4 to 6 MB, with L2 associativity increased from 16-way to 24-way. Cut-down versions with 3 MB L2 also exist, which are commonly called Penryn-3M and Wolfdale-3M as well as Yorkfield-6M, respectively. The single-core version of Penryn, listed as Penryn-L here, is not a sepa ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
65 nm
The 65 nm process is an advanced lithographic node used in volume CMOS (MOSFET) semiconductor fabrication. Printed linewidths (i.e. transistor gate lengths) can reach as low as 25 nm on a nominally 65 nm process, while the pitch between two lines may be greater than 130 nm. Process node For comparison, cellular ribosomes are about 20 nm end-to-end. A crystal of bulk silicon has a lattice constant of 0.543 nm, so such transistors are on the order of 100 atoms across. By September 2007, Intel, AMD, IBM, UMC and Chartered were also producing 65 nm chips. While feature sizes may be drawn as 65 nm or less, the wavelengths of light used for lithography are 193 nm and 248 nm. Fabrication of sub-wavelength features requires special imaging technologies, such as optical proximity correction and phase-shifting masks. The cost of these techniques adds substantially to the cost of manufacturing sub-wavelength semiconductor products, with the ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Pentium 4
Pentium 4 is a series of single-core central processing unit, CPUs for Desktop computer, desktops, laptops and entry-level Server (computing), servers manufactured by Intel. The processors were shipped from November 20, 2000 until August 8, 2008. All Pentium 4 CPUs are based on the NetBurst microarchitecture, the successor to the P6 (microarchitecture), P6. The Pentium 4 #Willamette, Willamette (180 nm) introduced SSE2, while the #Prescott, Prescott (90 nm) introduced SSE3 and later 64-bit technology. Later versions introduced Hyper-threading, Hyper-Threading Technology (HTT). The first Pentium 4-branded processor to implement x86-64, 64-bit was the Prescott (90 nm) (February 2004), but this feature was not enabled. Intel subsequently began selling 64-bit Pentium 4s using the ''"E0" revision'' of the Prescotts, being sold on the OEM market as the Pentium 4, model F. The E0 revision also adds eXecute Disable (XD) (Intel's name for the NX bit) to Intel 64. Int ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
90 nm
The 90 nm process refers to the technology used in semiconductor manufacturing to create integrated circuits with a minimum feature size of 90 nanometers. It was an advancement over the previous 130 nm process. Eventually, it was succeeded by smaller process nodes, such as the 65 nm, 45 nm, and 32 nm processes. It was commercialized by the 2003–2005 timeframe, by semiconductor companies including Toshiba, Sony, Samsung, IBM, Intel, Fujitsu, TSMC, Elpida, AMD, Infineon, Texas Instruments and Micron Technology. The origin of the 90 nm value is historical; it reflects a trend of 70% scaling every 2–3 years. The naming is formally determined by the International Technology Roadmap for Semiconductors (ITRS). The 300 mm wafer size became mainstream at the 90 nm node. The previous wafer size was 200 mm diameter. The 193 nm wavelength was introduced by many (but not all) companies for lithography of critical layers mainly during the 90 nm node. Y ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
CMOS
Complementary metal–oxide–semiconductor (CMOS, pronounced "sea-moss ", , ) is a type of MOSFET, metal–oxide–semiconductor field-effect transistor (MOSFET) semiconductor device fabrication, fabrication process that uses complementary and symmetrical pairs of p-type semiconductor, p-type and n-type semiconductor, n-type MOSFETs for logic functions. CMOS technology is used for constructing integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips (including Nonvolatile BIOS memory, CMOS BIOS), and other digital logic circuits. CMOS technology is also used for analog circuits such as image sensors (CMOS sensors), data conversion, data converters, RF circuits (RF CMOS), and highly integrated transceivers for many types of communication. In 1948, Bardeen and Brattain patented an insulated-gate transistor (IGFET) with an inversion layer. Bardeen's concept forms the basis of CMOS technology today. The CMOS process was presented by Fairchild Semico ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
