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Freescale S08
The 9S08 (68HCS08 or S08 for short) is an 8-bit microcontroller (μC) family originally produced by Motorola, later by Freescale Semiconductor, and currently by NXP, descended from the Motorola 6800 microprocessor. It is a CISC microcontroller. A slightly extended variant of the 68HC08, it shares upward compatibility with the aging 68HC05 microcontrollers, and is found in almost any type of embedded systems. The larger members offer up to 128 KiB of flash, and 8 KiB of RAM via a simple memory management unit (MMU) which allows bank-switching 16 KiB of the address space and an address/data register pair which allows data fetches from any address. The paging scheme used allows for a theoretical maximum of 4 MB of flash. MMU-equipped variants offer two extra CPU instructions, CALL and RTC, which are used instead of JSR and RTS respectively when dealing with subroutines placed in paged memory, allowing direct page-to-page subroutine calls. In a single at ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Freescale 68HC08
The 68HC08 (also abbreviated as HC08) is a broad family of 8-bit microcontrollers from Motorola Semiconductor (later from Freescale then NXP). HC08's are fully code-compatible with their predecessors, the Motorola 68HC05. Like all Motorola processors that share lineage from the 6800, they use the von Neumann architecture as well as memory-mapped I/O. This family has five CPU registers that are not part of the memory. One 8-bit accumulator A, a 16-bit index register H:X, a 16-bit stack pointer SP, a 16-bit program counter PC, and an 8-bit condition code register CCR. Some instructions refer to the different bytes in the H:X index register independently. Among the HC08's there are dozens of processor families, each targeted to different embedded applications. Features and capabilities vary widely, from 8 to 64-pin processors, from LIN connectivity to USB Universal Serial Bus (USB) is an industry standard, developed by USB Implementers Forum (USB-IF), for digital ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
8-bit
In computer architecture, 8-bit integers or other data units are those that are 8 bits wide (1 octet). Also, 8-bit central processing unit (CPU) and arithmetic logic unit (ALU) architectures are those that are based on registers or data buses of that size. Memory addresses (and thus address buses) for 8-bit CPUs are generally larger than 8-bit, usually 16-bit. 8-bit microcomputers are microcomputers that use 8-bit microprocessors. The term '8-bit' is also applied to the character sets that could be used on computers with 8-bit bytes, the best known being various forms of extended ASCII, including the ISO/IEC 8859 series of national character sets especially Latin 1 for English and Western European languages. The IBM System/360 introduced byte-addressable memory with 8-bit bytes, as opposed to bit-addressable or decimal digit-addressable or word-addressable memory, although its general-purpose registers were 32 bits wide, and addresses were contained in the lower 24 bits ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Opcode
In computing, an opcode (abbreviated from operation code) is an enumerated value that specifies the operation to be performed. Opcodes are employed in hardware devices such as arithmetic logic units (ALUs), central processing units (CPUs), and software instruction sets. In ALUs, the opcode is directly applied to circuitry via an input signal bus. In contrast, in CPUs, the opcode is the portion of a machine language instruction that specifies the operation to be performed. CPUs Opcodes are found in the machine language instructions of CPUs as well as in some abstract computing machines. In CPUs, an opcode may be referred to as an instruction machine code, instruction code, instruction syllable, instruction parcel, or opstring. For any particular processor (which may be a general CPU or a more specialized processing unit), the opcodes are defined by the processor's instruction set architecture (ISA). They can be described using an opcode table. The types of operations may in ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Motorola Microcontrollers
Motorola, Inc. () was an American multinational telecommunications company based in Schaumburg, Illinois. It was founded by brothers Paul and Joseph Galvin in 1928 and had been named Motorola since 1947. Many of Motorola's products had been radio-related communication equipment such as two-way radios, consumer walkie-talkies, cellular infrastructure, mobile phones, satellite communicators, pagers, as well as cable modems and semiconductors. After having lost $4.3 billion from 2007 to 2009, Motorola was split into two independent public companies: Motorola Solutions (its legal successor) and Motorola Mobility (spun off), on January 4, 2011. Motorola designed and sold wireless network equipment such as cellular transmission base stations and signal amplifiers. Its business and government customers consisted mainly of wireless voice and broadband systems (used to build private networks), and public safety communications systems like Astro and Dimetra. Motorola's home and broadc ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
CodeWarrior
CodeWarrior is an integrated development environment (IDE) published by NXP Semiconductors for editing, compiling, and debugging software for several microcontrollers and microprocessors (NXP ColdFire, Freescale ColdFire, ColdFire+, Kinetis, Qorivva, PX, Freescale RS08, Freescale S08, and S12Z) and digital signal controllers (DSC MC56F80X and MC5680XX) used in embedded systems. The system was developed by Metrowerks on the Macintosh, and was among the first development systems on that platform to cleanly support both the existing Motorola 68k and the PowerPC (PPC) instruction set architectures. During Apple's transition to PowerPC, CodeWarrior quickly became the ''de facto'' standard development system for the Mac, rapidly displacing NortonLifeLock, Symantec's THINK C and Apple's own Macintosh Programmer's Workshop. Apple's purchase of NeXT in 1996 led to a decline in CodeWarrior's relevance as Mac programming moved to the NeXT platform's own developer tools: Interface Builder and ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Small Device C Compiler
The Small Device C Compiler (SDCC) is a free-software, partially retargetable C compiler for 8-bit microcontrollers. It is distributed under the GNU General Public License. The package also contains an assembler, linker, simulator and debugger. SDCC is a popular open-source C compiler for microcontrollers compatible with Intel 8051/MCS-51. Supported hosts Sources, documentation, and binaries are available for Linux (32-bit and 64-bit), macOS (PPC and 64-bit), and Windows (32-bit and 64-bit). Supported targets The following include binary compatible derivatives: * Intel 8031, 8032, 8051, 8052; Maxim/Dallas DS80C390; C8051 * Motorola/Freescale/ NXP 68HC08 and S08 * Padauk PDK14 and PDK15 * Sharp SM83, the CPU found in the Nintendo Game Boy LR35902 SoC * STMicroelectronics STM8 * Zilog Z80, Z180, eZ80 in Z80 mode; Rabbit Semiconductor 2000, 2000A, 3000, 3000A, 4000, 6000; Toshiba TLCS-90; Z80N ( ZX Spectrum Next processor), R800. * MOS Technology 6502, WDC 65C02. Work ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
CAN Bus
A controller area network bus (CAN bus) is a vehicle bus standard designed to enable efficient communication primarily between electronic control units (ECUs). Originally developed to reduce the complexity and cost of electrical wiring in automobiles through multiplexing, the CAN bus protocol has since been adopted in various other contexts. This Broadcasting (networking), broadcast-based, Message passing, message-oriented protocol ensures data integrity and prioritization through a process called Arbiter (electronics), arbitration, allowing the highest priority device to continue transmitting if multiple devices attempt to send data simultaneously, while others back off. Its reliability is enhanced by Differential signalling, differential signaling, which mitigates electrical noise. Common versions of the CAN protocol include CAN 2.0, CAN FD, and CAN XL which vary in their data rate capabilities and maximum data payload sizes. History Development of the CAN Bus (computing), ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Interrupt Handler
In computer systems programming, an interrupt handler, also known as an interrupt service routine (ISR), is a special block of code associated with a specific interrupt condition. Interrupt handlers are initiated by hardware interrupts, software interrupt instructions, or software exception handling, exceptions, and are used for implementing device drivers or transitions between protected modes of operation, such as system calls. The traditional form of interrupt handler is the hardware interrupt handler. Hardware interrupts arise from electrical conditions or low-level protocols implemented in digital logic, are usually dispatched via a hard-coded table of interrupt vectors, asynchronously to the normal execution stream (as interrupt masking levels permit), often using a separate stack, and automatically entering into a different execution context (privilege level) for the duration of the interrupt handler's execution. In general, hardware interrupts and their handlers are used ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Program Counter
The program counter (PC), commonly called the instruction pointer (IP) in Intel x86 and Itanium microprocessors, and sometimes called the instruction address register (IAR), the instruction counter, or just part of the instruction sequencer, is a processor register that indicates where a computer is in its program sequence. Usually, the PC is incremented after fetching an instruction, and holds the memory address of (" points to") the next instruction that would be executed. Processors usually fetch instructions sequentially from memory, but ''control transfer'' instructions change the sequence by placing a new value in the PC. These include branches (sometimes called jumps), subroutine calls, and returns. A transfer that is conditional on the truth of some assertion lets the computer follow a different sequence under different conditions. A branch provides that the next instruction is fetched from elsewhere in memory. A subroutine call not only branches but saves the ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Stack Pointer
A stack register is a computer central processor register whose purpose is to keep track of a call stack. On an accumulator-based architecture machine, this may be a dedicated register. On a machine with multiple general-purpose registers, it may be a register that is reserved by convention, such as on the IBM System/360 through z/Architecture architecture and RISC architectures, or it may be a register that procedure call and return instructions are hardwired to use, such as on the PDP-11, VAX, and Intel x86 architectures. Some designs such as the Data General Eclipse had no dedicated register, but used a reserved hardware memory address for this function. Machines before the late 1960s—such as the PDP-8 and HP 2100—did not have compilers which supported recursion. Their subroutine instructions typically would save the current location in the jump address, and then set the program counter to the ''next'' address. While this is simpler than maintaining a stack, sin ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
16-bit
16-bit microcomputers are microcomputers that use 16-bit microprocessors. A 16-bit register can store 216 different values. The range of integer values that can be stored in 16 bits depends on the integer representation used. With the two most common representations, the range is 0 through 65,535 (216 − 1) for representation as an ( unsigned) binary number, and −32,768 (−1 × 215) through 32,767 (215 − 1) for representation as two's complement. Since 216 is 65,536, a processor with 16-bit memory addresses can directly access 64 KB (65,536 bytes) of byte-addressable memory. If a system uses segmentation with 16-bit segment offsets, more can be accessed. As of 2025, 16-bit microcontrollers cost well under a dollar (similar to close in price legacy 8-bit); the cheapest 16-bit microcontrollers cost less than other types including any 8-bit (and are more powerful, and easier to program generally), making 8-bit legacy microcontrollers not worth it for new applicatio ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
