The X
OR gate
A ⋅ B ¯ + A ¯ ⋅ B displaystyle Acdot overline B + overline A cdot B and ( A + B ) ⋅ displaystyle (A+B)cdot ( A ¯ + B ¯ displaystyle overline A + overline B ) both represent the X
OR gate
CMOS XOR gate Contents 1 Symbols 2 Passgatelogic wiring 3 Alternatives 4 More than two inputs 5 Applications 5.1 Uses in addition 5.2 Pseudorandom number generation 5.3 Correlation and sequence detection 6 See also 7 References 8 External links Symbols[edit] There are two symbols for XOR gates: the traditional symbol and the IEEE symbol. For more information see Logic Gate Symbols. Traditional XOR Symbol IEEE XOR Symbol The logic symbols ⊕, Jpq, and ⊻ can be used to denote XOR in
algebraic expressions.
Clike languages use the caret symbol ^ to denote bitwise XOR. (Note
that the caret does not denote logical conjunction (AND) in these
languages, despite the similarity of symbol.)
Passgatelogic wiring[edit]
An X
OR gate
Transmission Gate Logic wiring of an XOR gate Note: The "Rss" resistor prevents shunting current directly from "A"
and "B" to the output. Without it, if the circuit that provides inputs
A and B does not have the proper driving capability, the output might
not swing rail to rail or be severely slewrate limited. The "Rss"
resistor also limits the current from Vdd to ground which protects the
transistors and saves energy when the transistors are transitioning
between states.
Alternatives[edit]
If a specific type of gate is not available, a circuit that implements
the same function can be constructed from other available gates. A
circuit implementing an XOR function can be trivially constructed from
an XN
OR gate
A ⋅ B ¯ + A ¯ ⋅ B displaystyle Acdot overline B + overline A cdot B , we can construct an X
OR gate
X
OR gate
As an alternative, if different gates are available we can apply
Boolean algebra
A ⋅ B ¯ + A ¯ ⋅ B ≡ ( A + B ) ⋅ displaystyle Acdot overline B + overline A cdot Bequiv (A+B)cdot ( A ¯ + B ¯ ) displaystyle ( overline A + overline B ) as stated above, and apply de Morgan's Law to the last term to get ( A + B ) ⋅ displaystyle (A+B)cdot ( A ⋅ B ) ¯ displaystyle overline (Acdot B) which can be implemented using only three gates as shown on the
right.
An X
OR gate
( A + B ) ⋅ displaystyle (A+B)cdot ( A ¯ + B ¯ ) displaystyle ( overline A + overline B ) (noting from de Morgan's Law that a N
OR gate
Desired gate NAND construction NOR construction For the NAND constructions, the upper arrangement requires fewer
gates. For the NOR constructions, the lower arrangement offers the
advantage of a shorter propagation delay (the time delay between an
input changing and the output changing).
More than two inputs[edit]
Strict reading of the definition of exclusive or, or observation of
the IEC rectangular symbol, raises the question of correct behaviour
with additional inputs. If a logic gate were to accept three or more
inputs and produce a true output if exactly one of those inputs were
true, then it would in effect be a onehot detector (and indeed this
is the case for only two inputs). However, it is rarely implemented
this way in practice.
It is most common to regard subsequent inputs as being applied through
a cascade of binary exclusiveor operations: the first two signals are
fed into an XOR gate, then the output of that gate is fed into a
second X
OR gate
Example half adder circuit diagram Example full adder circuit diagram Pseudorandom number generation[edit]
Pseudorandom number (PRN) generators, specifically Linear feedback
shift registers, are defined in terms of the exclusiveor operation.
Hence, a suitable setup of XOR gates can model a linear feedback shift
register, in order to generate random numbers.
Correlation and sequence detection[edit]
XOR gates produce a 0 when both inputs match. When searching for a
specific bit pattern or PRN sequence in a very long data sequence, a
series of XOR gates can be used to compare a string of bits from the
data sequence against the target sequence in parallel. The number of 0
outputs can then be counted to determine how well the data sequence
matches the target sequence. Correlators are used in many
communications devices such as
CDMA
1110100101 (data) 11010 (target) 00111 (XOR) 2 zero bits 1110100101 11010 00000 5 zero bits 1110100101 11010 01110 2 zero bits 1110100101 11010 10011 2 zero bits 1110100101 11010 01000 4 zero bits 1110100101 11010 11111 0 zero bits Matches by offset: . : : : : : : :  0 1 2 3 4 5 In this example, the best match occurs when the target sequence is offset by 1 bit and all five bits match. When offset by 5 bits, the sequence exactly matches its inverse. By looking at the difference between the number of ones and zeros that come out of the bank of XOR gates, it is easy to see where the sequence occurs and whether or not it is inverted. Longer sequences are easier to detect than short sequences. See also[edit] Exclusive or AND gate OR gate Inverter (NOT gate) NAND gate NOR gate XNOR gate IMPLY gate Boolean algebra Logic gate Wikimedia Commons has media related to XOR gates. References[edit] ^ Fletcher, William (1980). An engineering approach to digital design. PrenticeHall. p. 98. ISBN 0132776995. ^ "A comparative performance analysis of various CMOS design techniques for XOR and XNOR circuits: Fig. 7. High performance transmission gate XOR, XNOR circuits" Archived March 4, 2016, at the Wayback Machine.. ^ "Designing combinational logic gates in CMOS". p. 233 ^ "Transmission Gate XOR". ^ "transmissiongate XOR (tiny XOR)" (via [1]) ^ "Figure 3, Exclusive OR and XNOR gate". ^ "PassTransistor Logic: Transmission Gate XOR" (p. 11) ^ 74LVC1G386 data sheet External links[edit] Interactive XOR Gate, Demonstrate the logic flow of the XOR Gate circuit created with Teahlab's simulator. v t e Logical connectives Tautology/True ⊤ displaystyle top Alternative denial (NAND gate) ↑ displaystyle uparrow Converse implication ← displaystyle leftarrow Implication (IMPLY gate) → displaystyle rightarrow Disjunction (OR gate) ∨ displaystyle lor Negation (NOT gate) ¬ displaystyle neg Exclusive or (XOR gate) ↮ displaystyle nleftrightarrow Biconditional (XNOR gate) ↔ displaystyle leftrightarrow Statement Joint denial (NOR gate) ↓ displaystyle downarrow Nonimplication ↛ displaystyle nrightarrow Converse nonimplication ↚ displaystyle nleftarrow Conjunction (AND gate) ∧ displaystyle land Contradiction/False ⊥
