A wafer, also called a slice or substrate, is a thin slice of semiconductor material, such as a crystalline silicon, used in electronics for the fabrication of integrated circuits and in photovoltaics for conventional, wafer-based solar cells. The wafer serves as the substrate for microelectronic devices built in and over the wafer and undergoes many microfabrication process steps such as doping or ion implantation, etching, deposition of various materials, and photolithographic patterning. Finally, the individual microcircuits are separated (dicing) and packaged.
1 History 2 Formation 3 Cleaning, texturing and etching 4 Wafer properties
4.1 Standard wafer sizes
4.1.1 Historical increases of wafer size 4.1.2 Proposed 450 mm transition
4.2 Analytical die count estimation
5 Compound semiconductors 6 See also 7 References 8 External links
This section needs expansion. You can help by adding to it. (January 2015)
By 1960, silicon wafers were being manufactured in the U.S. by companies such as MEMC/SunEdison. In 1965, American engineers Eric O. Ernst, Donald J. Hurd, and Gerard Seeley, while working under IBM, filed Patent US3423629A for the first high-capacity epitaxial apparatus. Formation See also: Boule (crystal)
The Czochralski process.
Wafers are formed of highly pure (99.9999999% purity), nearly
defect-free single crystalline material. One process for forming
crystalline wafers is known as Czochralski growth invented by the
Polish chemist Jan Czochralski. In this process, a cylindrical ingot
of high purity mono crystalline semiconductor, such as silicon or
germanium, called a boule, is formed by pulling a seed crystal from a
'melt'. Donor impurity atoms, such as boron or phosphorus in the
case of silicon, can be added to the molten intrinsic material in
precise amounts in order to dope the crystal, thus changing it into
n-type or p-type extrinsic semiconductor.
The boule is then sliced with a wafer saw (wire saw) and polished to
form wafers. The size of wafers for photovoltaics is
100–200 mm square and the thickness is 200–300 μm. In
the future, 160 μm will be the standard.
2-inch (51 mm), 4-inch (100 mm), 6-inch (150 mm), and 8-inch (200 mm) wafers
1-inch (25 mm) 2-inch (51 mm). Thickness 275 µm. 3-inch (76 mm). Thickness 375 µm. 4-inch (100 mm). Thickness 525 µm. 5-inch (130 mm) or 125 mm (4.9 inch). Thickness 625 µm. 150 mm (5.9 inch, usually referred to as "6 inch"). Thickness 675 µm. 200 mm (7.9 inch, usually referred to as "8 inch"). Thickness 725 µm. 300 mm (11.8 inch, usually referred to as "12 inch"). Thickness 775 µm. 450 mm (17.7 inch). Thickness 925 µm (proposed).
Wafers grown using materials other than silicon will have different
thicknesses than a silicon wafer of the same diameter. Wafer thickness
is determined by the mechanical strength of the material used; the
wafer must be thick enough to support its own weight without cracking
Historical increases of wafer size
A unit wafer fabrication step, such as an etch step, can produce more
chips proportional to the increase in wafer area, while the cost of
the unit fabrication step goes up more slowly than the wafer area.
This was the cost basis for increasing wafer size. Conversion to
300 mm wafers from 200 mm wafers began in earnest in 2000,
and reduced the price per die about 30-40%. However, this was not
without significant problems for the industry.
Proposed 450 mm transition
There is considerable resistance to the 450 mm transition despite
the possible productivity improvement, because of concern about
insufficient return on investment. Higher cost semiconductor
fabrication equipment for larger wafers increases the cost of
450 mm fabs (semiconductor fabrication facilities or factories).
Lithographer Chris Mack claimed in 2012 that the overall price per die
for 450 mm wafers would be reduced by only 10–20% compared to
300 mm wafers, because over 50% of total wafer processing costs
are lithography-related. Converting to larger 450 mm wafers would
reduce price per die only for process operations such as etch where
cost is related to wafer count, not wafer area. Cost for processes
such as lithography is proportional to wafer area, and larger wafers
would not reduce the lithography contribution to die cost. Nikon
plans to deliver 450-mm lithography equipment in 2015, with volume
production in 2017. In November 2013 ASML paused development
of 450-mm lithography equipment, citing uncertain timing of chipmaker
The time-line for 450 mm has not been fixed. Mark Durcan, CEO of
Micron Technology, said in February 2014 that he expects 450 mm
adoption to be delayed indefinitely or discontinued. “I am not
convinced that 450mm will ever happen but, to the extent that it does,
it’s a long way out in the future. There is not a lot of necessity
for Micron, at least over the next five years, to be spending a lot of
money on 450mm. There is a lot of investment that needs to go on in
the equipment community to make that happen. And the value at the end
of the day – so that customers would buy that equipment – I think
is dubious.” As of March 2014,
Wafermap showing fully patterned dies, and partially patterned dies which don't fully lie within the wafer.
Nevertheless, the number of gross die per wafer (DPW) can be estimated starting with the first-order approximation or wafer-to-die area ratio,
D P W =
displaystyle DPW=leftlfloor frac pi d^ 2 4S rightrfloor
is the wafer diameter (typically in mm) and
the size of each die (mm2). This formula simply states that the number of dies which can fit on the wafer cannot exceed the area of the wafer divided by the area of each individual die. It will always overestimate the true best-case gross DPW, since it includes the area of partially patterned dies which do not fully lie on the wafer surface (see figure). These partially patterned dies don't represent complete ICs, so they cannot be sold as functional parts. Refinements of this simple formula typically add an edge correction, to account for partial dies on the edge, which in general will be more significant when the area of the die is large compared to the total area of the wafer. In the other limiting case (infinitesimally small dies or infinitely large wafers), the edge correction is negligible. The correction factor or correction term generally takes one of the forms cited by De Vries,
D P W =
displaystyle DPW= frac displaystyle pi d^ 2 4S - frac displaystyle pi d sqrt 2S
(area ratio - circumference/(die diagonal length)) or
D P W =
exp ( − 2
displaystyle DPW=left( frac displaystyle pi d^ 2 4S right)exp(-2 sqrt S /d)
(area ratio scaled by an exponential factor) or
D P W =
displaystyle DPW= frac displaystyle pi d^ 2 4S left(1- frac displaystyle 2 sqrt S d right)^ 2
(area ratio scaled by a polynomial factor)
Studies comparing these analytical formulas to brute-force computational results show that the formulas can be made more accurate, over practical ranges of die sizes and aspect ratios, by adjusting the coefficients of the corrections to values above or below unity, and by replacing the linear die dimension
displaystyle sqrt S
( H + W )
(average side length) in the case of dies with large aspect ratio:
D P W =
displaystyle DPW= frac displaystyle pi d^ 2 4S -0.58^ * frac displaystyle pi d sqrt S
D P W =
exp ( −
displaystyle DPW=left( frac displaystyle pi d^ 2 4S right)exp(-2.32^ * sqrt S /d)
D P W =
displaystyle DPW= frac displaystyle pi d^ 2 4S left(1- frac displaystyle 1.16^ * sqrt S d right)^ 2
Diamond Cubic Crystal Structure, Silicon unit cell
Flats can be used to denote doping and crystallographic orientation. Red represents material that has been removed.
Wafers are grown from crystal having a regular crystal structure, with
silicon having a diamond cubic structure with a lattice spacing of
5.430710 Å (0.5430710 nm). When cut into wafers, the surface
is aligned in one of several relative directions known as crystal
orientations. Orientation is defined by the
Rapid thermal processing
Silicon on insulator
^ Phillip A. Laplante (2005). Comprehensive dictionary of electrical
engineering (2nd ed.). CRC Press. ISBN 978-0-8493-3086-5.
^ "Semi" SemiSource 2006: A supplement to Semiconductor International.
December 2005. Reference Section: How to Make a Chip. Adapted from
Design News. Reed
Wikimedia Commons has media related to Wafers.
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