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SPARC, for Scalable Processor Architecture, is a reduced instruction set computing (RISC) instruction set architecture (ISA) originally developed by Sun Microsystems. Its design was strongly influenced by the experimental Berkeley RISC system developed in the early 1980s. First released in 1987, SPARC
SPARC
was one of the most successful early commercial RISC systems, and its success led to the introduction of similar RISC designs from a number of vendors through the 1980s and 90s. The first implementation of the original 32-bit
32-bit
architecture (SPARC V7) was used in Sun's Sun-4 workstation and server systems, replacing their earlier Sun-3
Sun-3
systems based on the Motorola 68000 series
Motorola 68000 series
of processors. SPARC
SPARC
V8 added a number of improvements that were part of the SuperSPARC
SuperSPARC
series of processors released in 1992. SPARC
SPARC
V9, released in 1993, introduced a 64-bit architecture and was first released in Sun's UltraSPARC
UltraSPARC
processors in 1995. Later, SPARC processors were used in SMP and CC-NUMA servers produced by Sun, Solbourne and Fujitsu, among others. The design was turned over to the SPARC
SPARC
International trade group in 1989, and since then its architecture has been developed by its members. SPARC
SPARC
International is also responsible for licensing and promoting the SPARC
SPARC
architecture, managing SPARC
SPARC
trademarks (including SPARC, which it owns), and providing conformance testing. SPARC International was intended to grow the SPARC
SPARC
architecture to create a larger ecosystem; SPARC
SPARC
has been licensed to several manufacturers, including Atmel, Bipolar Integrated Technology, Cypress Semiconductor, Fujitsu, Matsushita and Texas Instruments. Due to SPARC
SPARC
International, SPARC
SPARC
is fully open, non-proprietary and royalty-free. By September 2017, the latest commercial high-end SPARC
SPARC
processors are Fujitsu's SPARC64 XII (introduced in 2017 for its SPARC
SPARC
M12 server) and SPARC64 XIfx (introduced in 2015 for its PRIMEHPC FX100 supercomputer); and Oracle's SPARC
SPARC
M8 (introduced in September 2017 for its high-end servers). On Friday, September 1, 2017, after a round of layoffs that started in Oracle Labs in November 2016, Oracle terminated SPARC
SPARC
design after the completion of the M8. Many of the processor core development group in Austin, Texas, was dismissed, as were the teams in Santa Clara, California, and Burlington, Vermont.[1][2] SPARC
SPARC
development continues with Fujitsu
Fujitsu
returning to the role of leading provider of SPARC servers, with a new CPU due in the 2020 time frame.[3]

Contents

1 Features 2 History 3 SPARC
SPARC
architecture licensees 4 Implementations 5 Operating system
Operating system
support 6 Open source
Open source
implementations 7 Supercomputers 8 See also 9 References 10 External links

Features[edit] The SPARC
SPARC
architecture was heavily influenced by the earlier RISC designs, including the RISC I and II from the University of California, Berkeley and the IBM 801. These original RISC designs were minimalist, including as few features or op-codes as possible and aiming to execute instructions at a rate of almost one instruction per clock cycle. This made them similar to the MIPS architecture in many ways, including the lack of instructions such as multiply or divide. Another feature of SPARC
SPARC
influenced by this early RISC movement is the branch delay slot. The SPARC
SPARC
processor usually contains as many as 160 general purpose registers. According to the "Oracle SPARC
SPARC
Architecture 2015" specification an "implementation may contain from 72 to 640 general-purpose 64-bit" registers.[4] At any point, only 32 of them are immediately visible to software — 8 are a set of global registers (one of which, g0, is hard-wired to zero, so only seven of them are usable as registers) and the other 24 are from the stack of registers. These 24 registers form what is called a register window, and at function call/return, this window is moved up and down the register stack. Each window has 8 local registers and shares 8 registers with each of the adjacent windows. The shared registers are used for passing function parameters and returning values, and the local registers are used for retaining local values across function calls. The "Scalable" in SPARC
SPARC
comes from the fact that the SPARC specification allows implementations to scale from embedded processors up through large server processors, all sharing the same core (non-privileged) instruction set. One of the architectural parameters that can scale is the number of implemented register windows; the specification allows from three to 32 windows to be implemented, so the implementation can choose to implement all 32 to provide maximum call stack efficiency, or to implement only three to reduce cost and complexity of the design, or to implement some number between them. Other architectures that include similar register file features include Intel i960, IA-64, and AMD 29000. The architecture has gone through several revisions. It gained hardware multiply and divide functionality in Version 8.[5][6] 64-bit (addressing and data) were added to the version 9 SPARC
SPARC
specification published in 1994.[7] In SPARC
SPARC
Version 8, the floating point register file has 16 double-precision registers. Each of them can be used as two single-precision registers, providing a total of 32 single precision registers. An odd-even number pair of double precision registers can be used as a quad-precision register, thus allowing 8 quad precision registers. SPARC
SPARC
Version 9 added 16 more double precision registers (which can also be accessed as 8 quad precision registers), but these additional registers can not be accessed as single precision registers. No SPARC
SPARC
CPU implements quad-precision operations in hardware as of 2004.[8] Tagged add and subtract instructions perform adds and subtracts on values checking that the bottom two bits of both operands are 0 and reporting overflow if they are not. This can be useful in the implementation of the run time for ML, Lisp, and similar languages that might use a tagged integer format. The endianness of the 32-bit
32-bit
SPARC
SPARC
V8 architecture is purely big-endian. The 64-bit SPARC
SPARC
V9 architecture uses big-endian instructions, but can access data in either big-endian or little-endian byte order, chosen either at the application instruction (load-store) level or at the memory page level (via an MMU setting). The latter is often used for accessing data from inherently little-endian devices, such as those on PCI buses. History[edit] There have been three major revisions of the architecture. The first published version was the 32-bit
32-bit
SPARC
SPARC
Version 7 (V7) in 1986. SPARC Version 8 (V8), an enhanced SPARC
SPARC
architecture definition, was released in 1990. The main differences between V7 and V8 were the addition of integer multiply and divide instructions, and an upgrade from 80-bit "extended precision" floating-point arithmetic to 128-bit "quad-precision" arithmetic. SPARC
SPARC
V8 served as the basis for IEEE Standard 1754-1994, an IEEE
IEEE
standard for a 32-bit
32-bit
microprocessor architecture. SPARC
SPARC
Version 9, the 64-bit SPARC
SPARC
architecture, was released by SPARC International in 1993. It was developed by the SPARC
SPARC
Architecture Committee consisting of Amdahl Corporation, Fujitsu, ICL, LSI Logic, Matsushita, Philips, Ross Technology, Sun Microsystems, and Texas Instruments. Newer specifications always remain compliant with the full SPARC
SPARC
V9 Level 1 specification. In 2002, the SPARC
SPARC
Joint Programming Specification 1 (JPS1) was released by Fujitsu
Fujitsu
and Sun, describing processor functions which were identically implemented in the CPUs of both companies ("Commonality"). The first CPUs conforming to JPS1 were the UltraSPARC
UltraSPARC
III by Sun and the SPARC64 V
SPARC64 V
by Fujitsu. Functionalities which are not covered by JPS1 are documented for each processor in "Implementation Supplements". At the end of 2003, JPS2 was released to support multicore CPUs. The first CPUs conforming to JPS2 were the UltraSPARC
UltraSPARC
IV by Sun and the SPARC64 VI
SPARC64 VI
by Fujitsu. In early 2006, Sun released an extended architecture specification, UltraSPARC
UltraSPARC
Architecture 2005. This includes not only the non-privileged and most of the privileged portions of SPARC
SPARC
V9, but also all the architectural extensions developed through the processor generations of UltraSPARC
UltraSPARC
III, IV, IV+ as well as CMT extensions starting with the UltraSPARC
UltraSPARC
T1 implementation:

the VIS 1 and VIS 2 instruction set extensions and the associated GSR register multiple levels of global registers, controlled by the GL register Sun's 64-bit MMU architecture privileged instructions ALLCLEAN, OTHERW, NORMALW, and INVALW access to the VER register is now hyperprivileged the SIR instruction is now hyperprivileged

In 2007, Sun released an updated specification, UltraSPARC Architecture 2007, to which the UltraSPARC
UltraSPARC
T2 implementation complied. In August 2012, Oracle Corporation
Oracle Corporation
made available a new specification, Oracle SPARC
SPARC
Architecture 2011, which besides the overall update of the reference, adds the VIS 3 instruction set extensions and hyperprivileged mode to the 2007 specification.[9] In October 2015, Oracle released SPARC
SPARC
M7, the first processor based on the new Oracle SPARC
SPARC
Architecture 2015 specification.[4]-[10] This revision includes VIS 4 instruction set extensions. SPARC
SPARC
architecture has provided continuous application binary compatibility from the first SPARC
SPARC
V7 implementation in 1987 through the Sun UltraSPARC
UltraSPARC
Architecture implementations. Among various implementations of SPARC, Sun's SuperSPARC
SuperSPARC
and UltraSPARC-I were very popular, and were used as reference systems for SPEC CPU95 and CPU2000 benchmarks. The 296 MHz UltraSPARC-II is the reference system for the SPEC CPU2006 benchmark. SPARC
SPARC
architecture licensees[edit] The following organizations have licensed the SPARC
SPARC
architecture:

Afara Websystems Bipolar Integrated Technology (BIT) Cypress Semiconductor European Space Research and Technology Center
European Space Research and Technology Center
(ESTEC) Fujitsu
Fujitsu
(and its Fujitsu
Fujitsu
Microelectronics subsidiary) Gaisler Research HAL Computer Systems Hyundai LSI Logic Matra Harris Semiconductors (MHS) Matsushita Electrical Industrial Co. Meiko Scientific Metaflow Technologies Philips
Philips
Electronics Prisma Ross Technology Solbourne Computer Systems & Processes Engineering Corporation
Corporation
(SPEC) TEMIC Weitek

Implementations[edit]

Name (codename) Model Frequency (MHz) Arch. version Year Total threads[note 1] Process (nm) Transistors (millions) Die size (mm2) IO pins Power (W) Voltage (V) L1 Dcache (KB) L1 Icache (KB) L2 cache (KB) L3 cache (KB)

SPARC (various), including MB86900[note 2] 14.28–40 V7 1987–1992 1×1=1 800–1300 ~0.1–1.8 -- 160–256 -- -- 0–128 (unified) none none

micro SPARC
SPARC
I (Tsunami) TI TMS390S10 40–50 V8 1992 1×1=1 800 0.8 225? 288 2.5 5 2 4 none none

SuperSPARC
SuperSPARC
I (Viking) TI TMX390Z50 / Sun STP1020 33–60 V8 1992 1×1=1 800 3.1 -- 293 14.3 5 16 20 0–2048 none

SPARClite Fujitsu
Fujitsu
MB8683x 66–108 V8E 1992 1×1=1 -- -- -- 144, 176 -- 2.5/3.3–5.0 V, 2.5–3.3 V 1, 2, 8, 16 1, 2, 8, 16 none none

hyper SPARC
SPARC
(Colorado 1) Ross RT620A 40–90 V8 1993 1×1=1 500 1.5 -- -- -- 5? 0 8 128–256 none

micro SPARC
SPARC
II (Swift) Fujitsu
Fujitsu
MB86904 / Sun STP1012 60–125 V8 1994 1×1=1 500 2.3 233 321 5 3.3 8 16 none none

hyper SPARC
SPARC
(Colorado 2) Ross RT620B 90–125 V8 1994 1×1=1 400 1.5 -- -- -- 3.3 0 8 128–256 none

SuperSPARC
SuperSPARC
II (Voyager) Sun STP1021 75–90 V8 1994 1×1=1 800 3.1 299 -- 16 -- 16 20 1024–2048 none

hyper SPARC
SPARC
(Colorado 3) Ross RT620C 125–166 V8 1995 1×1=1 350 1.5 -- -- -- 3.3 0 8 512–1024 none

TurboSPARC Fujitsu
Fujitsu
MB86907 160–180 V8 1996 1×1=1 350 3.0 132 416 7 3.5 16 16 512 none

UltraSPARC
UltraSPARC
(Spitfire) Sun STP1030 143–167 V9 1995 1×1=1 470 3.8 315 521 30[note 3] 3.3 16 16 512–1024 none

UltraSPARC
UltraSPARC
(Hornet) Sun STP1030 200 V9 1995 1×1=1 420 5.2 265 521 -- 3.3 16 16 512–1024 none

hyper SPARC
SPARC
(Colorado 4) Ross RT620D 180–200 V8 1996 1×1=1 350 1.7 -- -- -- 3.3 16 16 512 none

SPARC64 Fujitsu
Fujitsu
(HAL) 101–118 V9 1995 1×1=1 400 -- Multichip 286 50 3.8 128 128 -- --

SPARC64 II Fujitsu
Fujitsu
(HAL) 141–161 V9 1996 1×1=1 350 -- Multichip 286 64 3.3 128 128 -- --

SPARC64 III Fujitsu
Fujitsu
(HAL) MBCS70301 250–330 V9 1998 1×1=1 240 17.6 240 -- -- 2.5 64 64 8192 --

UltraSPARC
UltraSPARC
IIs (Blackbird) Sun STP1031 250–400 V9 1997 1×1=1 350 5.4 149 521 25[note 4] 2.5 16 16 1024 or 4096 none

UltraSPARC
UltraSPARC
IIs (Sapphire-Black) Sun STP1032 / STP1034 360–480 V9 1999 1×1=1 250 5.4 126 521 21[note 5] 1.9 16 16 1024–8192 none

UltraSPARC
UltraSPARC
IIi (Sabre) Sun SME1040 270–360 V9 1997 1×1=1 350 5.4 156 587 21 1.9 16 16 256–2048 none

UltraSPARC
UltraSPARC
IIi (Sapphire-Red) Sun SME1430 333–480 V9 1998 1×1=1 250 5.4 -- 587 21[note 6] 1.9 16 16 2048 none

UltraSPARC
UltraSPARC
IIe (Hummingbird) Sun SME1701 400–500 V9 1999 1×1=1 180 Al -- -- 370 13[note 7] 1.5–1.7 16 16 256 none

UltraSPARC
UltraSPARC
IIi (IIe+) (Phantom) Sun SME1532 550–650 V9 2000 1×1=1 180 Cu -- -- 370 17.6 1.7 16 16 512 none

SPARC64 GP Fujitsu
Fujitsu
SFCB81147 400–563 V9 2000 1×1=1 180 30.2 217 -- -- 1.8 128 128 8192 --

SPARC64 GP -- 600–810 V9 -- 1×1=1 150 30.2 -- -- -- 1.5 128 128 8192 --

SPARC64 IV Fujitsu
Fujitsu
MBCS80523 450–810 V9 2000 1×1=1 130 -- -- -- -- -- 128 128 2048 --

UltraSPARC
UltraSPARC
III (Cheetah) Sun SME1050 600 JPS1 2001 1×1=1 180 Al 29 330 1368 53 1.6 64 32 8192 none

UltraSPARC
UltraSPARC
III (Cheetah) Sun SME1052 750–900 JPS1 2001 1×1=1 130 Al 29 -- 1368 -- 1.6 64 32 8192 none

UltraSPARC
UltraSPARC
III Cu (Cheetah+) Sun SME1056 1002–1200 JPS1 2001 1×1=1 130 Cu 29 232 1368 80[note 8] 1.6 64 32 8192 none

UltraSPARC
UltraSPARC
IIIi (Jalapeño) Sun SME1603 1064–1593 JPS1 2003 1×1=1 130 87.5 206 959 52 1.3 64 32 1024 none

SPARC64 V
SPARC64 V
(Zeus) Fujitsu 1100–1350 JPS1 2003 1×1=1 130 190 289 269 40 1.2 128 128 2048 --

SPARC64 V+ (Olympus-B) Fujitsu 1650–2160 JPS1 2004 1×1=1 90 400 297 279 65 1 128 128 4096 --

UltraSPARC
UltraSPARC
IV (Jaguar) Sun SME1167 1050–1350 JPS2 2004 1×2=2 130 66 356 1368 108 1.35 64 32 16384 none

UltraSPARC
UltraSPARC
IV+ (Panther) Sun SME1167A 1500–2100 JPS2 2005 1×2=2 90 295 336 1368 90 1.1 64 64 2048 32768

UltraSPARC
UltraSPARC
T1 (Niagara) Sun SME1905 1000–1400 UA2005 2005 4×8=32 90 300 340 1933 72 1.3 8 16 3072 none

SPARC64 VI
SPARC64 VI
(Olympus-C) Fujitsu 2150–2400 JPS2 2007 2×2=4 90 540 422 -- 120–150 1.1 128×2 128×2 4096–6144 none

UltraSPARC
UltraSPARC
T2 (Niagara 2) Sun SME1908A 1000–1600 UA2007 2007 8×8=64 65 503 342 1831 95 1.1–1.5 8 16 4096 none

UltraSPARC
UltraSPARC
T2 Plus (Victoria Falls) Sun SME1910A 1200–1600 UA2007 2008 8×8=64 65 503 342 1831 - - 8 16 4096 none

SPARC64 VII
SPARC64 VII
(Jupiter)[11] Fujitsu 2400–2880 JPS2 2008 2×4=8 65 600 445 -- 150 -- 64×4 64×4 6144 none

UltraSPARC
UltraSPARC
"RK" (Rock)[12] Sun SME1832 2300 ???? canceled[13] 2×16=32 65 ? 396 2326 ? ? 32 32 2048 ?

SPARC64 VIIIfx
SPARC64 VIIIfx
(Venus)[14][15] Fujitsu 2000 JPS2 / HPC-ACE 2009 1×8=8 45 760 513 1271 58 ? 32×8 32×8 6144 none

LEON2FT Atmel
Atmel
AT697F 100 V8 2009 1×1=1 180 -- -- 196 1 1.8/3.3 16 32 -- none

SPARC T3
SPARC T3
(Rainbow Falls) Oracle/Sun 1650 UA2007 2010 8×16=128 40[16] ???? 371 ? 139 ? 8 16 6144 none

Galaxy FT-1500 NUDT (China) 1800 UA2007? 201? 8×16=128 40 ???? ??? ? 65 ? 16×16 16×16 512×16 4096

SPARC64 VII+
SPARC64 VII+
(Jupiter-E or M3)[17][18] Fujitsu 2667–3000 JPS2 2010 2×4=8 65 - - - 160 - 64×4 64×4 12288 none

LEON3FT Cobham Gaisler GR712RC 100 V8E 2011 1×2=2 180 - - - 1.5[note 9] 1.8/3.3 4x4Kb 4x4Kb none none

R1000 MCST (Russia) 1000 JPS2 2011 1×4=4 90 180 128 - 15 1, 1.8, 2.5 32 16 2048 none

SPARC T4
SPARC T4
(Yosemite Falls)[19] Oracle 2850–3000 OSA2011 2011 8×8=64 40 855 403 ? 240 ? 16×8 16×8 128×8 4096

SPARC64 IXfx[20][21][22] Fujitsu 1850 JPS2 / HPC-ACE 2012 1x16=16 40 1870 484 1442 110 ? 32×16 32×16 12288 none

SPARC64 X
SPARC64 X
(Athena)[23] Fujitsu 2800 OSA2011 / HPC-ACE 2012 2×16=32 28 2950 587.5 1500 270 ? 64×16 64×16 24576 none

SPARC
SPARC
T5 Oracle 3600 OSA2011 2013 8×16=128 28 1500 478 ? ? ? 16×16 16×16 128×16 8192

SPARC
SPARC
M5[24] Oracle 3600 OSA2011 2013 8×6=48 28 3900 511 ? ? ? 16×6 16×6 128×6 49152

SPARC
SPARC
M6[25] Oracle 3600 OSA2011 2013 8×12=96 28 4270 643 ? ? ? 16×12 16×12 128×12 49152

SPARC64 X+
SPARC64 X+
(Athena+)[26] Fujitsu 3200–3700 OSA2011 / HPC-ACE 2014 2×16=32 28 2990 600 1500 392 ? 64×16 64×16 24M none

SPARC64 XIfx[27] Fujitsu 2200 JPS2 / HPC-ACE2 2014 1×(32+2)=34 20 3750 ? 1001 ? ? 64×34 64×34 12M×2 none

SPARC
SPARC
M7[28][29] Oracle 4133 OSA2015 2015 8×32=256 20 >10,000 ? ? ? ? 16×32 16×32 256×24 65536

SPARC
SPARC
S7[30][31] Oracle 4270 OSA2015 2016 8×8=64 20 ???? ? ? ? ? 16×8 16×8 256×2+256×4 16384

SPARC64 XII[32] Fujitsu 4250 OSA201? / HPC-ACE 2017 8×12=96 20 5500 795 1860 ? ? 64×12 64×12 512×12 32768

SPARC
SPARC
M8[33][34] Oracle 5000 OSA2017 2017 8×32=256 20 ? ? ? ? ? 32×32 16×32 128×32+256×8 65536

LEON4 Cobham Gaisler GR740 250 [note 10] V8E 2017 1×4=4 32 - - - - 1.2/2.5/3.3 4x4 4x4 2048 none

Name (codename) Model Frequency (MHz) Arch. version Year Total threads[note 1] Process (nm) Transistors (millions) Die size (mm2) IO pins Power (W) Voltage (V) L1 Dcache (KB) L1 Icache (KB) L2 cache (KB) L3 cache (KB)

Notes:

^ a b Threads per core × number of cores ^ Various SPARC
SPARC
V7 implementations were produced by Fujitsu, LSI Logic, Weitek, Texas Instruments, Cypress and Temic. A SPARC
SPARC
V7 processor generally consisted of several discrete chips, usually comprising an integer unit (IU), a floating-point unit (FPU), a memory management unit (MMU) and cache memory. Conversely, the Atmel
Atmel
(now Microchip Technology) TSC695 is a single-chip SPARC
SPARC
V7 implementation. ^ @167 MHz ^ @250 MHz ^ @400 MHz ^ @440 MHz ^ max. @500 MHz ^ @900 MHz ^ excluding I/O buses ^ nominal; specification from 100 to 424 MHz depending on attached RAM capabilities

Operating system
Operating system
support[edit] SPARC
SPARC
machines have generally used Sun's SunOS, Solaris, OpenSolaris or derived as illumos, but other operating systems such as NeXTSTEP, RTEMS, FreeBSD, OpenBSD, NetBSD, and Linux
Linux
have also been used. In 1993, Intergraph
Intergraph
announced a port of Windows NT
Windows NT
to the SPARC architecture,[35] but it was later cancelled. In October 2015, Oracle announced a " Linux
Linux
for SPARC
SPARC
reference platform".[36] Open source
Open source
implementations[edit] Several fully open source implementations of the SPARC
SPARC
architecture exist:

LEON, a 32-bit, SPARC
SPARC
Version 8 implementation, designed especially for space use. Source code
Source code
is written in VHDL, and licensed under the GPL. OpenSPARC T1, released in 2006, a 64-bit, 32-thread implementation conforming to the UltraSPARC
UltraSPARC
Architecture 2005 and to SPARC
SPARC
Version 9 (Level 1). Source code
Source code
is written in Verilog, and licensed under many licenses. Most OpenSPARC T1 source code is licensed under the GPL. Source based on existent open source projects will continue to be licensed under their current licenses. Binary programs are licensed under a binary software license agreement. S1, a 64-bit Wishbone compliant CPU core based on the OpenSPARC T1 design. It is a single UltraSPARC
UltraSPARC
v9 core capable of 4-way SMT. Like the T1, the source code is licensed under the GPL. OpenSPARC T2, released in 2008, a 64-bit, 64-thread implementation conforming to the UltraSPARC
UltraSPARC
Architecture 2007 and to SPARC
SPARC
Version 9 (Level 1). Source code
Source code
is written in Verilog, and licensed under many licenses. Most OpenSPARC T2 source code is licensed under the GPL. Source based on existing open source projects will continue to be licensed under their current licenses. Binary programs are licensed under a binary Software License Agreement.

A fully open source simulator for the SPARC
SPARC
architecture also exists:

RAMP Gold, a 32-bit, 64-thread SPARC
SPARC
Version 8 implementation, designed for FPGA-based architecture simulation. RAMP Gold is written in ~36,000 lines of SystemVerilog, and licensed under the BSD licenses.

Supercomputers[edit] For HPC loads Fujitsu
Fujitsu
builds specialized SPARC64 fx processors with a new instruction extensions set, called HPC-ACE (High Performance Computing — Arithmetic Computational Extensions). Fujitsu's K computer
K computer
ranked No. 1 in TOP500 — June 2011 and November 2011 lists. It combines 88,128 SPARC64 VIIIfx
SPARC64 VIIIfx
CPUs, each with eight cores, for a total of 705,024 cores — almost twice as many as any other system in the TOP500
TOP500
at that time. The K Computer was more powerful than the next five systems on the list combined, and had the highest performance-to-power ratio of any other supercomputer system.[37] It also ranked No. 6 in Green500 — June 2011 list, with a score of 824.56 MFLOPS/W.[38] In the November 2012 release of TOP500, the K computer
K computer
ranked No. 3, using by far the most power of the top three.[39] It ranked No. 85 on the corresponding Green500
Green500
release.[40] Newer HPC processors, IXfx and XIfx, were included in recent PRIMEHPC FX10 and FX100 supercomputers. Tianhe-2
Tianhe-2
( TOP500
TOP500
No. 1 as of November 2014[41]) has a number of nodes with Galaxy FT-1500 OpenSPARC-based processors developed in China. However, those processors did not contribute to the LINPACK score.[42][43] See also[edit]

ERC32 — based on SPARC
SPARC
V7 specification Ross Technology, Inc. — a SPARC
SPARC
microprocessor developer during the 1980s and 1990s Sparcle — a modified SPARC
SPARC
with multiprocessing support used by the MIT Alewife project LEON — a space rated SPARC
SPARC
V8 processor. R1000 — a Russian quad-core microprocessor based on SPARC
SPARC
V9 specification Galaxy FT-1500 — a Chinese 16-core OpenSPARC based processor

References[edit]

^ Steven J. Vaughan-Nichols (September 5, 2017). "Sun set: Oracle closes down last Sun product lines". ZDNet.  ^ Shaun Nichols (August 31, 2017). "Oracle finally decides to stop prolonging the inevitable, begins hardware layoffs". The Register.  ^ " SPARC
SPARC
AND SOLARIS, THE PAST AND THE FUTURE - Tales from the Datacenter". Tales from the Datacenter. 2017-10-30. Retrieved 2018-01-23.  ^ a b "Oracle SPARC
SPARC
Architecture 2015: One Architecture ... Multiple Innovative Implementations" (PDF). Draft D1.0.0. January 12, 2016. Retrieved June 13, 2016. IMPL. DEP. #2-V8: An Oracle SPARC Architecture implementation may contain from 72 to 640 general-purpose 64-bit R registers. This corresponds to a grouping of the registers into MAXPGL + 1 sets of global R registers plus a circular stack of N_REG_WINDOWS sets of 16 registers each, known as register windows. The number of register windows present (N_REG_WINDOWS) is implementation dependent, within the range of 3 to 32 (inclusive).  ^ " SPARC
SPARC
Options", Using the GNU
GNU
Compiler Collection (GCC), GNU, retrieved January 8, 2013  ^ SPARC
SPARC
Optimizations With GCC, OSNews, February 23, 2004, retrieved January 8, 2013  ^ Weaver, D. L.; Germond, T., eds. (1994), "The SPARC
SPARC
Architecture Manual, Version 9" (PDF), SPARC
SPARC
International, Inc., Prentice Hall, ISBN 0-13-825001-4, retrieved December 6, 2011  ^ " SPARC
SPARC
Behavior and Implementation". Numerical Computation Guide – Sun Studio 10. Sun Microsystems, Inc. 2004. Retrieved September 24, 2011. There are four situations, however, when the hardware will not successfully complete a floating-point instruction: ... The instruction is not implemented by the hardware (such as ... quad-precision instructions on any SPARC
SPARC
FPU).  ^ "Oracle SPARC
SPARC
Architecture 2011" (PDF), Oracle Corporation, May 21, 2014, retrieved November 25, 2015  ^ John Soat. " SPARC
SPARC
M7 Innovation". Oracle web site. Oracle Corporation. Retrieved October 13, 2015.  ^ FX1 Key Features & Specifications (PDF), Fujitsu, February 19, 2008, retrieved December 6, 2011  ^ Tremblay, Marc; Chaudhry, Shailender (February 19, 2008), "A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT SPARC(R) Processor" (PDF), OpenSPARC, Sun Microsystems, retrieved December 6, 2011  ^ Vance, Ashlee (June 15, 2009), "Sun Is Said to Cancel Big Chip Project", The New York Times, retrieved May 23, 2010  ^ " Fujitsu
Fujitsu
shows off SPARC64 VII", heise online, August 28, 2008, retrieved December 6, 2011  ^ Barak, Sylvie (May 14, 2009), " Fujitsu
Fujitsu
unveils world's fastest CPU", The Inquirer, retrieved December 6, 2011  ^ "Sparc T3 processor" (PDF), Oracle Corporation, retrieved December 6, 2011  ^ Morgan, Timothy Prickett (December 3, 2010), "Ellison: Sparc T4 due next year", The Register, retrieved December 6, 2011  ^ " SPARC Enterprise
SPARC Enterprise
M-series Servers Architecture" (PDF), Fujitsu, April 2011  ^ Morgan, Timothy Prickett (August 22, 2011), "Oracle's Sparc T4 chip", The Register, retrieved December 6, 2011  ^ Morgan, Timothy Prickett (November 21, 2011), " Fujitsu
Fujitsu
parades 16-core Sparc64 super stunner", The Register, retrieved December 8, 2011  ^ " Fujitsu
Fujitsu
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SPARC
products" (PDF). oracle.com. Retrieved August 29, 2017.  ^ " Fujitsu
Fujitsu
Presentation pdf" (PDF). fujitsu.com. Retrieved August 29, 2017.  ^ " Fujitsu
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v t e

Reduced instruction set computer
Reduced instruction set computer
(RISC) architectures

Berkeley RISC IBM 801 Stanford MIPS

Active

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POWER PowerPC Cell

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Historic

Alpha AMD Am29000 Apollo PRISM Atmel
Atmel
AVR32 Clipper CRISP DEC Prism Intel i860 Intel i960 MIPS-X Motorola 88000 PA-RISC ROMP

v t e

Computer hardware
Computer hardware
by Sun Microsystems
Sun Microsystems
(acquired by Oracle Corporation, 2010)

Processors

SPARC MB86900 microSPARC SuperSPARC UltraSPARC UltraSPARC
UltraSPARC
II

UltraSPARC
UltraSPARC
IIe UltraSPARC
UltraSPARC
IIi Gemini

UltraSPARC
UltraSPARC
III

UltraSPARC
UltraSPARC
III Cu UltraSPARC
UltraSPARC
IIIi

UltraSPARC
UltraSPARC
IV UltraSPARC
UltraSPARC
T1 UltraSPARC
UltraSPARC
T2 SPARC
SPARC
T3 SPARC
SPARC
T4 SPARC
SPARC
T5 Rock MAJC

Workstations and servers

Sun-1 Sun-2 Sun-3 Sun386i Sun-4 SPARCstation/server/center Netra Ultra Enterprise Sun Blade Sun Fire Java Workstation SPARC
SPARC
Enterprise

Network computers

JavaStation Sun Ray

Storage hardware

StorageTek 5800 Sun Fire
Sun Fire
X4500

Other

Sun Modular Datacenter Sun SPOT Sun Neptune

v t e

Oracle Corporation

Corporate directors

Jeffrey Berg H. Raymond Bingham Michael Boskin Safra Catz Larry Ellison Héctor García-Molina Joseph Grundfest Jeffrey O. Henley Mark Hurd Jack F. Kemp Donald L. Lucas Naomi O. Seligman

Acquisitions (list)

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DBMS

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Programming languages

Java PL/SQL

IDE

JDeveloper Forms NetBeans Apex SQL Developer Developer Studio

Middleware

Fusion Middleware WebCenter SOA Suite WebLogic Server Coherence Tuxedo GlassFish

Operating systems

Oracle Linux Oracle Solaris

Computer hardware

Sun Fire SPARC
SPARC
(T-Series, Enterprise) StorageTek

Computer appliances

Oracle Exadata Oracle Exalogic Big Data Appliance

Education and recognition

Oracle Certification Program

Category Commons

v t e

CPU technologies

Architecture

Turing machine Post–Turing machine Universal Turing machine Quantum Turing machine Belt machine Stack machine Register machine Counter machine Pointer machine Random access machine Random access stored program machine Finite-state machine Queue automaton Von Neumann Harvard (modified) Dataflow TTA Cellular Artificial neural network

Machine learning Deep learning Neural processing unit (NPU)

Convolutional neural network Load/store architecture Register memory architecture Endianness FIFO Zero-copy NUMA HUMA HSA Mobile computing Surface computing Wearable computing Heterogeneous computing Parallel computing Concurrent computing Distributed computing Cloud computing Amorphous computing Ubiquitous computing Fabric computing Cognitive computing Unconventional computing Hypercomputation Quantum computing Adiabatic quantum computing Linear optical quantum computing Reversible computing Reverse computation Reconfigurable computing Optical computing Ternary computer Analogous computing Mechanical computing Hybrid computing Digital computing DNA computing Peptide computing Chemical computing Organic computing Wetware computing Neuromorphic computing Symmetric multiprocessing
Symmetric multiprocessing
(SMP) Asymmetric multiprocessing
Asymmetric multiprocessing
(AMP) Cache hierarchy Memory hierarchy

ISA types

ASIP CISC RISC EDGE (TRIPS) VLIW (EPIC) MISC OISC NISC ZISC Comparison

ISAs

x86 z/Architecture ARM MIPS Power Architecture
Power Architecture
(PowerPC) SPARC Mill Itanium
Itanium
(IA-64) Alpha Prism SuperH V850 Clipper VAX Unicore PA-RISC MicroBlaze RISC-V

Word size

1-bit 2-bit 4-bit 8-bit 9-bit 10-bit 12-bit 15-bit 16-bit 18-bit 22-bit 24-bit 25-bit 26-bit 27-bit 31-bit 32-bit 33-bit 34-bit 36-bit 39-bit 40-bit 48-bit 50-bit 60-bit 64-bit 128-bit 256-bit 512-bit Variable

Execution

Instruction pipelining

Bubble Operand forwarding

Out-of-order execution

Register renaming

Speculative execution

Branch predictor Memory dependence prediction

Hazards

Parallel level

Bit

Bit-serial Word

Instruction Pipelining

Scalar Superscalar

Task

Thread Process

Data

Vector

Memory

Multithreading

Temporal Simultaneous (SMT) (Hyper-threading) Speculative (SpMT) Preemptive Cooperative Clustered Multi-Thread (CMT) Hardware scout

Flynn's taxonomy

SISD SIMD
SIMD
(SWAR) SIMT MISD MIMD

SPMD

Addressing mode

CPU performance

Instructions per second (IPS) Instructions per clock (IPC) Cycles per instruction (CPI) Floating-point operations per second (FLOPS) Transactions per second (TPS) Synaptic Updates Per Second (SUPS) Performance per watt Orders of magnitude (computing) Cache performance measurement and metric

Core count

Single-core processor Multi-core processor Manycore processor

Types

Central processing unit
Central processing unit
(CPU) GPGPU AI accelerator Vision processing unit (VPU) Vector processor Barrel processor Stream processor Digital signal processor
Digital signal processor
(DSP) I/O processor/DMA controller Network processor Baseband processor Physics processing unit
Physics processing unit
(PPU) Coprocessor Secure cryptoprocessor ASIC FPGA FPOA CPLD Microcontroller Microprocessor Mobile processor Notebook processor Ultra-low-voltage processor Multi-core processor Manycore processor Tile processor Multi-chip module
Multi-chip module
(MCM) Chip stack multi-chip modules System on a chip
System on a chip
(SoC) Multiprocessor system-on-chip (MPSoC) Programmable System-on-Chip
System-on-Chip
(PSoC) Network on a chip (NoC)

Components

Execution unit (EU) Arithmetic logic unit
Arithmetic logic unit
(ALU) Address generation unit
Address generation unit
(AGU) Floating-point unit
Floating-point unit
(FPU) Load-store unit (LSU) Branch predictor Unified Reservation Station Barrel shifter Uncore Sum addressed decoder (SAD) Front-side bus Back-side bus Northbridge (computing) Southbridge (computing) Adder (electronics) Binary multiplier Binary decoder Address decoder Multiplexer Demultiplexer Registers Cache Memory management unit
Memory management unit
(MMU) Input–output memory management unit
Input–output memory management unit
(IOMMU) Integrated Memory Controller (IMC) Power Management Unit (PMU) Translation lookaside buffer
Translation lookaside buffer
(TLB) Stack engine Register file Processor register Hardware register Memory buffer register (MBR) Program counter Microcode
Microcode
ROM Datapath Control unit Instruction unit Re-order buffer Data buffer Write buffer Coprocessor Electronic switch Electronic circuit Integrated circuit Three-dimensional integrated circuit Boolean circuit Digital circuit Analog circuit Mixed-signal integrated circuit Power management integrated circuit Quantum circuit Logic gate

Combinational logic Sequential logic Emitter-coupled logic
Emitter-coupled logic
(ECL) Transistor–transistor logic
Transistor–transistor logic
(TTL) Glue logic

Quantum gate Gate array Counter (digital) Bus (computing) Semiconductor device Clock rate CPU multiplier Vision chip Memristor

Power management

APM ACPI Dynamic frequency scaling Dynamic voltage scaling Clock gating

Hardware security

Non-executable memory (NX bit) Memory Protection Extensions (Intel MPX) Intel Secure Key Hardware restriction (firmware) Software Guard Extensions (Intel SGX) Trusted Execution Technology Trusted Platform Module
Trusted Platform Module
(TPM) Secure cryptoprocessor Hardware security module Hengzhi chip

Related

History of general-

.