PCI Express (Peripheral Component Interconnect Express), officially
abbreviated as PCIe or PCI-e, is a high-speed serial computer
expansion bus standard, designed to replace the older PCI, PCI-X, and
AGP bus standards. PCIe has numerous improvements over the older
standards, including higher maximum system bus throughput, lower I/O
pin count and smaller physical footprint, better performance scaling
for bus devices, a more detailed error detection and reporting
mechanism (Advanced Error Reporting, AER), and native hot-swap
functionality. More recent revisions of the PCIe standard provide
hardware support for I/O virtualization.
PCI Express electrical interface is also used in a variety of
other standards, most notably the laptop expansion card interface
ExpressCard and computer storage interfaces
SATA Express and M.2.
Format specifications are maintained and developed by the
Special Interest Group), a group of more than 900 companies that also
maintain the conventional PCI specifications. PCIe 3.0 is the latest
standard for expansion cards that are in production and available on
mainstream personal computers.
1.3 Serial bus
2 Form factors
PCI Express (standard)
PCI Express Mini Card
2.2.1 Physical dimensions
2.2.2 Electrical interface
2.2.3 Mini-SATA (mSATA) variant
2.2.4 Mini PCIe v2
PCI Express External Cabling
2.4 Derivative forms
3 History and revisions
PCI Express 1.0a
PCI Express 1.1
PCI Express 2.0
PCI Express 2.1
PCI Express 3.0
PCI Express 3.1
PCI Express 4.0
PCI Express 5.0
3.9 Extensions and future directions
4 Hardware protocol summary
4.1 Physical layer
4.1.1 Data transmission
4.2 Data link layer
4.3 Transaction layer
5.1 External GPUs
5.2 Storage devices
5.3 Cluster interconnect
6 Competing protocols
7 See also
10 Further reading
11 External links
An example of the PCI Express topology; white "junction boxes"
represent PCI Express device downstream ports, while the gray
ones represent upstream ports.:7
PCI Express ×1 card containing a
PCI Express switch (covered by a
small heat sink), which creates multiple endpoints out of one endpoint
and allows it to be shared by multiple devices
PCI Express bus is a high-speed serial replacement
of the older PCI/
PCI-X bus. One of the key differences between the
PCI Express bus and the older PCI is the bus topology; PCI uses a
shared parallel bus architecture, in which the PCI host and all
devices share a common set of address, data and control lines. In
PCI Express is based on point-to-point topology, with
separate serial links connecting every device to the root complex
(host). Due to its shared bus topology, access to the older PCI bus is
arbitrated (in the case of multiple masters), and limited to one
master at a time, in a single direction. Furthermore, the older PCI
clocking scheme limits the bus clock to the slowest peripheral on the
bus (regardless of the devices involved in the bus transaction). In
PCI Express bus link supports full-duplex communication
between any two endpoints, with no inherent limitation on concurrent
access across multiple endpoints.
In terms of bus protocol,
PCI Express communication is encapsulated in
packets. The work of packetizing and de-packetizing data and
status-message traffic is handled by the transaction layer of the PCI
Express port (described later). Radical differences in electrical
signaling and bus protocol require the use of a different mechanical
form factor and expansion connectors (and thus, new motherboards and
new adapter boards); PCI slots and
PCI Express slots are not
interchangeable. At the software level,
PCI Express preserves backward
compatibility with PCI; legacy PCI system software can detect and
PCI Express devices without explicit support for the
PCI Express standard, though new
PCI Express features are
PCI Express link between two devices can consist of anywhere from
one to 32 lanes. In a multi-lane link, the packet data is striped
across lanes, and peak data throughput scales with the overall link
width. The lane count is automatically negotiated during device
initialization, and can be restricted by either endpoint. For example,
PCI Express (×1) card can be inserted into a multi-lane
slot (×4, ×8, etc.), and the initialization cycle auto-negotiates
the highest mutually supported lane count. The link can dynamically
down-configure itself to use fewer lanes, providing a failure
tolerance in case bad or unreliable lanes are present. The PCI Express
standard defines slots and connectors for multiple widths: ×1, ×4,
×8, ×12, ×16 and ×32.:4,5 This allows the
PCI Express bus to
serve both cost-sensitive applications where high throughput is not
needed, as well as performance-critical applications such as 3D
graphics, networking (
10 Gigabit Ethernet
10 Gigabit Ethernet or multiport Gigabit
Ethernet), and enterprise storage (SAS or Fibre Channel).
As a point of reference, a
PCI-X (133 MHz 64-bit) device and a
PCI Express 1.0 device using four lanes (×4) have roughly the
same peak single-direction transfer rate of 1064 MB/s. The PCI
Express bus has the potential to perform better than the
PCI-X bus in
cases where multiple devices are transferring data simultaneously, or
if communication with the
PCI Express peripheral is bidirectional.
PCI Express link between two devices consists of one or more lanes,
which are dual simplex channels using two differential signaling
PCI Express devices communicate via a logical connection called an
interconnect or link. A link is a point-to-point communication
channel between two
PCI Express ports allowing both of them to send
and receive ordinary PCI requests (configuration, I/O or memory
read/write) and interrupts (INTx, MSI or MSI-X). At the physical
level, a link is composed of one or more lanes. Low-speed
peripherals (such as an 802.11
Wi-Fi card) use a single-lane (×1)
link, while a graphics adapter typically uses a much wider and faster
A lane is composed of two differential signaling pairs, with one pair
for receiving data and the other for transmitting. Thus, each lane is
composed of four wires or signal traces. Conceptually, each lane is
used as a full-duplex byte stream, transporting data packets in
eight-bit "byte" format simultaneously in both directions between
endpoints of a link. Physical
PCI Express links may contain from
one to 32 lanes, more precisely 1, 2, 4, 8, 12, 16 or 32
lanes.:4,5 Lane counts are written with an "×" prefix (for
example, "×8" represents an eight-lane card or slot), with ×16 being
the largest size in common use. For mechanical card sizes, see
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The bonded serial bus architecture was chosen over the traditional
parallel bus due to inherent limitations of the latter, including
half-duplex operation, excess signal count, and inherently lower
bandwidth due to timing skew.
Timing skew results from separate
electrical signals within a parallel interface traveling through
conductors of different lengths, on potentially different printed
circuit board (PCB) layers, and at possibly different signal
velocities. Despite being transmitted simultaneously as a single word,
signals on a parallel interface have different travel duration and
arrive at their destinations at different times. When the interface
clock period is shorter than the largest time difference between
signal arrivals, recovery of the transmitted word is no longer
possible. Since timing skew over a parallel bus can amount to a few
nanoseconds, the resulting bandwidth limitation is in the range of
hundreds of megahertz.
A serial interface does not exhibit timing skew because there is only
one differential signal in each direction within each lane, and there
is no external clock signal since clocking information is embedded
within the serial signal itself. As such, typical bandwidth
limitations on serial signals are in the multi-gigahertz range. PCI
Express is one example of the general trend toward replacing parallel
buses with serial interconnects; other examples include Serial ATA
Serial Attached SCSI
Serial Attached SCSI (SAS),
FireWire (IEEE 1394), and
RapidIO. In digital video, examples in common use are DVI,
Multichannel serial design increases flexibility with its ability to
allocate fewer lanes for slower devices.
PCI Express (standard)
Various slots on a computer motherboard, from top to bottom:
PCI Express ×4
PCI Express ×16
PCI Express ×1
PCI Express ×16
Conventional PCI (32-bit, 5 V)
An open-ended PCI express ×1 slot
PCI Express card fits into a slot of its physical size or larger
(with ×16 as the largest used), but may not fit into a smaller PCI
Express slot; for example, a ×16 card may not fit into a ×4 or ×8
slot. Some slots use open-ended sockets to permit physically longer
cards and negotiate the best available electrical and logical
The number of lanes actually connected to a slot may also be fewer
than the number supported by the physical slot size. An example is a
×16 slot that runs at ×4, which will accept any ×1, ×2, ×4, ×8
or ×16 card, but provides only four lanes. Its specification may read
as "×16 (×4 mode)", while "×size @ ×speed" notation
("×16 @ ×4") is also common. The advantage is that such
slots can accommodate a larger range of
PCI Express cards without
requiring motherboard hardware to support the full transfer rate.
Standard mechanical sizes are ×1, ×4, ×8, and ×16. Cards with a
differing number of lanes need to use the next larger mechanical size
(ie. a ×2 card uses the ×4 size, or a ×12 card uses the ×16 size).
The cards themselves are designed and manufactured in various sizes.
For example, solid-state drives (SSDs) that come in the form of PCI
Express cards often use HHHL (half height, half length) and FHHL (full
height, half length) to describe the physical dimensions of the
The following table identifies the conductors on each side of the edge
connector on a
PCI Express card. The solder side of the printed
circuit board (PCB) is the A side, and the component side is the B
side. PRSNT1# and PRSNT2# pins must be slightly shorter than the
rest, to ensure that a hot-plugged card is fully inserted. The WAKE#
pin uses full voltage to wake the computer, but must be pulled high
from the standby power to indicate that the card is wake capable.
PCI Express connector pinout (×1, ×4, ×8 and ×16 variants)
Must connect to farthest PRSNT2# pin
Lane 8 transmit data, + and −
Main power pins
Lane 8 receive data, + and −
JTAG port pins
Lane 9 transmit data, + and −
Lane 9 receive data, + and −
Lane 10 transmit data, + and −
+3.3 V aux
Link reactivation; fundamental reset
Lane 10 receive data, + and −
Request running clock
Lane 11 transmit data, + and −
Reference clock differential pair
Lane 0 transmit data, + and −
Lane 11 receive data, + and −
Lane 0 receive data, + and −
Lane 12 transmit data, + and −
Lane 12 receive data, + and −
PCI Express ×1 cards end at pin 18
Lane 1 transmit data, + and −
Lane 13 transmit data, + and −
Lane 1 receive data, + and −
Lane 13 receive data, + and −
Lane 2 transmit data, + and −
Lane 14 transmit data, + and −
Lane 2 receive data, + and −
Lane 14 receive data, + and −
Lane 3 transmit data, + and −
Lane 15 transmit data, + and −
Lane 3 receive data, + and −
Lane 15 receive data, + and −
PCI Express ×4 cards end at pin 32
Lane 4 transmit data, + and −
Lane 4 receive data, + and −
Lane 5 transmit data, + and −
Lane 5 receive data, + and −
Lane 6 transmit data, + and −
Lane 6 receive data, + and −
Zero volt reference
Lane 7 transmit data, + and −
Supplies power to the PCIe card
Signal from the card to the motherboard
Lane 7 receive data, + and −
Signal from the motherboard to the card
May be pulled low or sensed by multiple cards
Tied together on card
PCI Express ×8 cards end at pin 49
Not presently used, do not connect
8-pin (left) and 6-pin (right) power connectors used on PCI Express
All PCI express cards may consume up to 7000300000000000000♠3 A
at 7000330000000000000♠+3.3 V
(7000990000000000000♠9.9 W). The amount of +12 V and total
power they may consume depends on the type of card::35–36
×1 cards are limited to 0.5 A at +12V (6 W) and 10 W
×4 and wider cards are limited to 2.1 A at +12V (25 W) and
25 W combined.
A full-sized ×1 card may draw up to the 25 W limits after
initialization and software configuration as a "high power device".
A full-sized ×16 graphics card may draw up to 5.5 A at +12V
(66 W) and 75 W combined after initialization and software
configuration as a "high power device".
Sense0 pin is connected to ground by the cable or power supply, or
float on board if cable is not connected.
Sense1 pin is connected to +12V by the cable or power supply, or float
on board if cable is not connected.
Optional connectors add 75 W (6-pin) or 150 W (8-pin) of
+12 V power for up to 300 W total (2×75 W +
1×150 W). Some cards are using two 8-pin connectors, but this
has not been standardized yet, therefore such cards must not carry the
PCI Express logo. This configuration allows 375 W total
(1×75 W + 2×150 W) and will likely be standardized by
PCI-SIG with the
PCI Express 4.0 standard. The 8-pin PCI Express
connector could be confused with the
EPS12V connector, which is mainly
used for powering SMP and multi-core systems.
6-pin power connector (75 W)
8-pin power connector (150 W)
6 pin power connector pin map
8 pin power connector pin map
Not connected (usually +12 V as well)
Sense1 (8-pin connected[a])
Sense0 (6-pin or 8-pin connected)
^ When a 6-pin connector is plugged into an 8-pin receptacle the card
is notified by a missing Sense1 that it may only use up to 75 W.
PCI Express Mini Card
PCI Express Mini Card and its connector
MiniPCI and Mini
PCI Express cards in comparison
PCI Express Mini Card (also known as
Mini PCI Express, Mini PCIe, Mini
PCI-E, mPCIe, and PEM), based on PCI Express, is a replacement for the
Mini PCI form factor. It is developed by the PCI-SIG. The host device
PCI Express and USB 2.0 connectivity, and each card
may use either standard. Most laptop computers built after 2005 use
PCI Express for expansion cards; however, as of 2015[update], many
vendors are moving toward using the newer
M.2 form factor for this
Due to different dimensions,
PCI Express Mini Cards are not physically
compatible with standard full-size
PCI Express slots; however, passive
adapters exist that allow them to be used in full-size slots.
PCI Express Mini Cards are 30 × 50.95 mm
(width × length) for a Full Mini Card. There is a 52-pin edge
connector, consisting of two staggered rows on a 0.8 mm pitch.
Each row has eight contacts, a gap equivalent to four contacts, then a
further 18 contacts. Boards have a thickness of 1.0 mm, excluding
the components. A "Half Mini Card" (sometimes abbreviated as HMC) is
also specified, having approximately half the physical length of
PCI Express Mini Card edge connectors provide multiple connections and
PCI Express ×1 (with SMBus)
Wires to diagnostics LEDs for wireless network (i.e., Wi-Fi) status on
SIM card for
WCDMA applications (UIM signals on spec.).
Future extension for another PCIe lane
1.5 V and 3.3 V power
Mini-SATA (mSATA) variant
Despite sharing the
Mini PCI Express form factor, an mSATA slot is not
necessarily electrically compatible with
Mini PCI Express. For this
reason, only certain notebooks are compatible with mSATA drives. Most
compatible systems are based on Intel's Sandy Bridge processor
architecture, using the Huron River platform. Notebooks like Lenovo's
ThinkPad T, W and X series, released in March–April 2011, have
support for an mSATA SSD card in their WWAN card slot. The ThinkPad
Edge E220s/E420s, and the Lenovo IdeaPad Y460/Y560/Y570/Y580 also
Some notebooks (notably the
Asus Eee PC, the Apple MacBook Air, and
Dell mini9 and mini10) use a variant of the
PCI Express Mini Card
as an SSD. This variant uses the reserved and several non-reserved
pins to implement SATA and IDE interface passthrough, keeping only
USB, ground lines, and sometimes the core PCIe ×1 bus intact.
This makes the "miniPCIe" flash and solid-state drives sold for
netbooks largely incompatible with true
PCI Express Mini
Also, the typical
Asus miniPCIe SSD is 71 mm long, causing the
Dell 51 mm model to often be (incorrectly) referred to as half
length. A true 51 mm Mini PCIe SSD was announced in 2009, with
two stacked PCB layers that allow for higher storage capacity. The
announced design preserves the PCIe interface, making it compatible
with the standard mini PCIe slot. No working product has yet been
Intel has numerous desktop boards with the PCIe ×1 Mini-Card slot
which typically do not support mSATA SSD. A list of desktop boards
that natively support mSATA in the PCIe ×1 Mini-Card slot (typically
multiplexed with a SATA port) is provided on the
Mini PCIe v2
Main article: M.2
The new version of
Mini PCI express,
M.2 replaces the mSATA standard.
Computer bus interfaces provided through the
M.2 connector are PCI
Express 3.0 (up to four lanes),
Serial ATA 3.0, and
USB 3.0 (a single
logical port for each of the latter two). It is up to the manufacturer
M.2 host or device to select which interfaces are to be
supported, depending on the desired level of host support and device
PCI Express External Cabling
PCI Express External Cabling (also known as External PCI Express,
Cabled PCI Express, or ePCIe) specifications were released by the
PCI-SIG in February 2007.
Standard cables and connectors have been defined for ×1, ×4, ×8,
and ×16 link widths, with a transfer rate of 250 MB/s per lane.
PCI-SIG also expects the norm will evolve to reach 500 MB/s,
PCI Express 2.0. An example of the uses of Cabled
PCI Express is
a metal enclosure, containing a number of PCI slots and PCI-to-ePCIe
adapter circuitry. This device would not be possible had it not been
for the ePCIe spec.
Several other types of expansion card are derived from PCIe; these
ExpressCard: Successor to the
PC Card form factor (with ×1 PCIe and
USB 2.0; hot-pluggable)
PCI Express ExpressModule: A hot-pluggable modular form factor defined
for servers and workstations
XQD card: A PCI Express-based flash card standard by the CompactFlash
XMC: Similar to the CMC/PMC form factor (VITA 42.3)
AdvancedTCA: A complement to
CompactPCI for larger applications;
supports serial based backplane topologies
AMC: A complement to the AdvancedTCA specification; supports processor
and I/O modules on ATCA boards (×1, ×2, ×4 or ×8 PCIe).
FeaturePak: A tiny expansion card format (43 × 65 mm) for
embedded and small-form-factor applications which implements two ×1
PCIe links on a high-density connector along with USB, I2C, and up to
100 points of I/O
Universal IO: A variant from Super Micro
Computer Inc designed for use
in low-profile rack-mounted chassis. It has the connector bracket
reversed so it cannot fit in a normal
PCI Express socket, but it is
pin-compatible and may be inserted if the bracket is removed.
Thunderbolt: A variant from
Intel that combines
DisplayPort and PCIe
protocols in a form factor compatible with Mini DisplayPort.
Thunderbolt 3.0 also combines
USB 3.1 and uses the
USB-C form factor
as opposed to Mini DisplayPort.
Serial Digital Video Out: Some 9xx series
Intel chipsets allow for
adding another output for the integrated video into a PCIe slot
(mostly dedicated and 16 lanes).
M.2 (formerly known as NGFF)
M-PCIe brings PCIe 3.0 to mobile devices (such as tablets and
smartphones), over the
M-PHY physical layer.
U.2 (formerly known as SFF-8639)
History and revisions
While in early development, PCIe was initially referred to as HSI (for
High Speed Interconnect), and underwent a name change to 3GIO (for 3rd
Generation I/O) before finally settling on its
PCI-SIG name PCI
Express. A technical working group named the Arapaho Work Group (AWG)
drew up the standard. For initial drafts, the AWG consisted only of
Intel engineers; subsequently the AWG expanded to include industry
PCI Express is a technology under constant development and
As of 2013[update],
PCI Express version 4 has been drafted with final
specifications expected in 2017. At the 2016 PCI SIG’s annual
developer’s conference and at the
Intel Developer Forum, Synopsys
showed a system running on PCIe 4.0, while
Mellanox provided an
appropriate network card.
PCI Express link performance
^ a b In each direction (each lane is a dual simplex channel).
^ Initially, 25.0 GT/s were also considered for technical
PCI Express 1.0a
PCI-SIG introduced PCIe 1.0a, with a per-lane data rate of
250 MB/s and a transfer rate of 2.5 gigatransfers per second
(GT/s). Transfer rate is expressed in transfers per second instead of
bits per second because the number of transfers includes the overhead
bits, which do not provide additional throughput; PCIe 1.x uses an
8b/10b encoding scheme, resulting in a 20% (= 2/10) overhead on
the raw channel bandwidth.
PCI Express 1.1
In 2005, PCI-SIG introduced PCIe 1.1. This updated specification
includes clarifications and several improvements, but is fully
PCI Express 1.0a. No changes were made to the data
PCI Express 2.0
A PCI Express 2.0 expansion card that provides USB 3.0
PCI-SIG announced the availability of the
PCI Express Base 2.0
specification on 15 January 2007. The PCIe 2.0 standard doubles
the transfer rate compared with PCIe 1.0 to 5 GT/s and the per-lane
throughput rises from 250 MB/s to 500 MB/s. Consequently, a
32-lane PCIe connector (×32) can support an aggregate throughput of
up to 16 GB/s.
PCIe 2.0 motherboard slots are fully backward compatible with PCIe
v1.x cards. PCIe 2.0 cards are also generally backward compatible with
PCIe 1.x motherboards, using the available bandwidth of PCI Express
1.1. Overall, graphic cards or motherboards designed for v2.0 will
work with the other being v1.1 or v1.0a.
PCI-SIG also said that PCIe 2.0 features improvements to the
point-to-point data transfer protocol and its software
Intel's first PCIe 2.0 capable chipset was the X38 and boards began to
ship from various vendors (Abit, Asus, Gigabyte) as of October 21,
2007. AMD started supporting PCIe 2.0 with its AMD 700 chipset
series and nVidia started with the MCP72. All of Intel's prior
chipsets, including the
Intel P35 chipset, supported PCIe 1.1 or
Like 1.x, PCIe 2.0 uses an
8b/10b encoding scheme, therefore
delivering, per-lane, an effective 4 Gbit/s max transfer rate
from its 5 GT/s raw data rate.
PCI Express 2.1
PCI Express 2.1 (with its specification dated March 4, 2009) supports
a large proportion of the management, support, and troubleshooting
systems planned for full implementation in
PCI Express 3.0. However,
the speed is the same as
PCI Express 2.0. The increase in power from
the slot breaks backward compatibility between
PCI Express 2.1 cards
and some older motherboards with 1.0/1.0a, but most motherboards with
PCI Express 1.1 connectors are provided with a
BIOS update by their
manufacturers through utilities to support backward compatibility of
cards with PCIe 2.1.
PCI Express 3.0
PCI Express 3.0 Base specification revision 3.0 was made available in
November 2010, after multiple delays. In August 2007, PCI-SIG
PCI Express 3.0 would carry a bit rate of 8
gigatransfers per second (GT/s), and that it would be backward
compatible with existing
PCI Express implementations. At that time, it
was also announced that the final specification for
PCI Express 3.0
would be delayed until Q2 2010. New features for the PCI Express
3.0 specification include a number of optimizations for enhanced
signaling and data integrity, including transmitter and receiver
equalization, PLL improvements, clock data recovery, and channel
enhancements for currently supported topologies.
Following a six-month technical analysis of the feasibility of scaling
PCI Express interconnect bandwidth, PCI-SIG's analysis found that
8 gigatransfers per second can be manufactured in mainstream silicon
process technology, and can be deployed with existing low-cost
materials and infrastructure, while maintaining full compatibility
(with negligible impact) to the
PCI Express protocol stack.
PCI Express 3.0 upgrades the encoding scheme to
8b/10b encoding, reducing the bandwidth overhead from 20%
of PCI Express 2.0 to approximately 1.54% (= 2/130). This is
achieved by XORing a known binary polynomial as a "scrambler" to the
data stream in a feedback topology. Because the scrambling polynomial
is known, the data can be recovered by running applying the
PCI Express 3.0's 8 GT/s bit rate effectively
delivers 985 MB/s per lane, nearly doubling the lane bandwidth
PCI Express 2.0.
On November 18, 2010, the PCI
Special Interest Group officially
published the finalized
PCI Express 3.0 specification to its members
to build devices based on this new version of PCI Express.
PCI Express 3.1
In September 2013, PCI Express 3.1 specification was announced to
be released in late 2013 or early 2014, consolidating various
improvements to the published PCI Express 3.0 specification in
three areas: power management, performance and functionality.
It was released in November 2014.
PCI Express 4.0
On November 29, 2011,
PCI-SIG preliminarily announced PCI Express
4.0, providing a 16 GT/s bit rate that doubles the bandwidth
PCI Express 3.0, while maintaining backward and forward
compatibility in both software support and used mechanical
PCI Express 4.0 specs will also bring OCuLink-2, an
alternative to Thunderbolt connector. OCuLink version 2 will have up
to 16 GT/s (8 GB/s total for ×4 lanes), while the maximum
bandwidth of a Thunderbolt 3 connector is 5 GB/s. Additionally, active
and idle power optimizations are to be investigated.
In August 2016,
Synopsys presented a test machine running PCIe 4.0 at
Intel Developer Forum. Their IP has been licensed to several firms
planning to present their chips and products at the end of 2016.
PCI Express 4.0 was officially announced on June 8, 2017, by
PCI-SIG. The spec includes improvements in flexibility,
scalability, and lower-power.
PCI Express 5.0
In June 2017,
PCI-SIG preliminarily announced the
PCI Express 5.0
specification. Bandwidth is expected to increase to 32 GT/s,
yielding 128 GB/s in full duplex networking configurations. It is
expected to be standardized in 2019.
Extensions and future directions
Some vendors offer PCIe over fiber products, but these
generally find use only in specific cases where transparent PCIe
bridging is preferable to using a more mainstream standard (such as
InfiniBand or Ethernet) that may require additional software to
support it; current implementations focus on distance rather than raw
bandwidth and typically do not implement a full ×16 link.
Thunderbolt was co-developed by
Intel and Apple as a general-purpose
high speed interface combining a ×4 PCIe link with
was originally intended to be an all-fiber interface, but due to early
difficulties in creating a consumer-friendly fiber interconnect,
nearly all implementations are copper systems. A notable exception,
the Sony VAIO Z VPC-Z2, uses a nonstandard
USB port with an optical
component to connect to an outboard PCIe display adapter. Apple has
been the primary driver of Thunderbolt adoption through 2011, though
several other vendors have announced new products and systems
Mobile PCIe specification (abbreviated to M-PCIe) allows PCI Express
architecture to operate over the MIPI Alliance's
M-PHY physical layer
technology. Building on top of already existing widespread adoption of
M-PHY and its low-power design, Mobile PCIe allows
PCI Express to be
used in tablets and smartphones.
OCuLink (standing for "optical-copper link", since Cu is the chemical
symbol for Copper) is an extension for the "cable version of PCI
Express", acting as a competitor to version 3 of the Thunderbolt
interface. Version 1.0 of OCuLink, released in Oct 2015, supports up
to PCIe 3.0 x4 lanes (8 GT/s, 3.9 GB/s) over copper cabling;
a fiber optic version may appear in the future.
Hardware protocol summary
The PCIe link is built around dedicated unidirectional couples of
serial (1-bit), point-to-point connections known as lanes. This is in
sharp contrast to the earlier PCI connection, which is a bus-based
system where all the devices share the same bidirectional, 32-bit or
64-bit parallel bus.
PCI Express is a layered protocol, consisting of a transaction layer,
a data link layer, and a physical layer. The Data Link Layer is
subdivided to include a media access control (MAC) sublayer. The
Physical Layer is subdivided into logical and electrical sublayers.
The Physical logical-sublayer contains a physical coding sublayer
(PCS). The terms are borrowed from the
IEEE 802 networking protocol
Card pins and lengths
2×18 = 36
2×7 = 14
2×32 = 64
2×21 = 42
2×49 = 98
2×38 = 76
2×82 = 164
2×71 = 142
PCI Express ×1 connector, allowing longer cards capable
of using more lanes to be plugged while operating at ×1 speeds
The PCIe Physical Layer (PHY, PCIEPHY,
PCI Express PHY, or PCIe PHY)
specification is divided into two sub-layers, corresponding to
electrical and logical specifications. The logical sublayer is
sometimes further divided into a MAC sublayer and a PCS, although this
division is not formally part of the PCIe specification. A
specification published by Intel, the PHY Interface for PCI Express
(PIPE), defines the MAC/PCS functional partitioning and the
interface between these two sub-layers. The PIPE specification also
identifies the physical media attachment (PMA) layer, which includes
the serializer/deserializer (SerDes) and other analog circuitry;
SerDes implementations vary greatly among ASIC vendors,
PIPE does not specify an interface between the PCS and PMA.
At the electrical level, each lane consists of two unidirectional LVDS
pairs operating at 2.5, 5, 8 or 16 Gbit/s, depending on the
negotiated capabilities. Transmit and receive are separate
differential pairs, for a total of four data wires per lane.
A connection between any two PCIe devices is known as a link, and is
built up from a collection of one or more lanes. All devices must
minimally support single-lane (×1) link. Devices may optionally
support wider links composed of 2, 4, 8, 12, 16, or 32 lanes. This
allows for very good compatibility in two ways:
A PCIe card physically fits (and works correctly) in any slot that is
at least as large as it is (e.g., an ×1 sized card will work in any
A slot of a large physical size (e.g., ×16) can be wired electrically
with fewer lanes (e.g., ×1, ×4, ×8, or ×12) as long as it provides
the ground connections required by the larger physical slot size.
In both cases, PCIe negotiates the highest mutually supported number
of lanes. Many graphics cards, motherboards and
BIOS versions are
verified to support ×1, ×4, ×8 and ×16 connectivity on the same
Even though the two would be signal-compatible, it is not usually
possible to place a physically larger PCIe card (e.g., a ×16 sized
card) into a smaller slot – though if the PCIe slots are
altered or a riser is used most motherboards will allow this. The
width of a PCIe connector is 8.8 mm, while the height is
11.25 mm, and the length is variable. The fixed section of the
connector is 11.65 mm in length and contains two rows of 11 (22
pins total), while the length of the other section is variable
depending on the number of lanes. The pins are spaced at 1 mm
intervals, and the thickness of the card going into the connector is
PCIe sends all control messages, including interrupts, over the same
links used for data. The serial protocol can never be blocked, so
latency is still comparable to conventional PCI, which has dedicated
Data transmitted on multiple-lane links is interleaved, meaning that
each successive byte is sent down successive lanes. The PCIe
specification refers to this interleaving as data striping. While
requiring significant hardware complexity to synchronize (or deskew)
the incoming striped data, striping can significantly reduce the
latency of the nth byte on a link. While the lanes are not tightly
synchronized, there is a limit to the lane to lane skew of
20/8/6 ns for 2.5/5/8 GT/s so the hardware buffers can
re-align the striped data. Due to padding requirements, striping
may not necessarily reduce the latency of small data packets on a
As with other high data rate serial transmission protocols, the clock
is embedded in the signal. At the physical level,
PCI Express 2.0
8b/10b encoding scheme to ensure that strings of
consecutive identical digits (zeros or ones) are limited in length.
This coding was used to prevent the receiver from losing track of
where the bit edges are. In this coding scheme every eight (uncoded)
payload bits of data are replaced with 10 (encoded) bits of transmit
data, causing a 20% overhead in the electrical bandwidth. To improve
the available bandwidth,
PCI Express version 3.0 instead uses
128b/130b encoding with scrambling.
128b/130b encoding relies on the
scrambling to limit the run length of identical-digit strings in data
streams and ensure the receiver stays synchronised to the transmitter.
It also reduces electromagnetic interference (EMI) by preventing
repeating data patterns in the transmitted data stream.
Data link layer
The data link layer performs three vital services for the PCIe express
sequence the transaction layer packets (TLPs) that are generated by
the transaction layer,
ensure reliable delivery of TLPs between two endpoints via an
acknowledgement protocol (ACK and NAK signaling) that explicitly
requires replay of unacknowledged/bad TLPs,
initialize and manage flow control credits
On the transmit side, the data link layer generates an incrementing
sequence number for each outgoing TLP. It serves as a unique
identification tag for each transmitted TLP, and is inserted into the
header of the outgoing TLP. A 32-bit cyclic redundancy check code
(known in this context as Link CRC or LCRC) is also appended to the
end of each outgoing TLP.
On the receive side, the received TLP's LCRC and sequence number are
both validated in the link layer. If either the LCRC check fails
(indicating a data error), or the sequence-number is out of range
(non-consecutive from the last valid received TLP), then the bad TLP,
as well as any TLPs received after the bad TLP, are considered invalid
and discarded. The receiver sends a negative acknowledgement message
(NAK) with the sequence-number of the invalid TLP, requesting
re-transmission of all TLPs forward of that sequence-number. If the
received TLP passes the LCRC check and has the correct sequence
number, it is treated as valid. The link receiver increments the
sequence-number (which tracks the last received good TLP), and
forwards the valid TLP to the receiver's transaction layer. An ACK
message is sent to remote transmitter, indicating the TLP was
successfully received (and by extension, all TLPs with past
If the transmitter receives a NAK message, or no acknowledgement (NAK
or ACK) is received until a timeout period expires, the transmitter
must retransmit all TLPs that lack a positive acknowledgement (ACK).
Barring a persistent malfunction of the device or transmission medium,
the link-layer presents a reliable connection to the transaction
layer, since the transmission protocol ensures delivery of TLPs over
an unreliable medium.
In addition to sending and receiving TLPs generated by the transaction
layer, the data-link layer also generates and consumes DLLPs, data
link layer packets. ACK and NAK signals are communicated via DLLPs, as
are some power management messages and flow control credit information
(on behalf of the transaction layer).
In practice, the number of in-flight, unacknowledged TLPs on the link
is limited by two factors: the size of the transmitter's replay buffer
(which must store a copy of all transmitted TLPs until the remote
receiver ACKs them), and the flow control credits issued by the
receiver to a transmitter.
PCI Express requires all receivers to issue
a minimum number of credits, to guarantee a link allows sending
PCIConfig TLPs and message TLPs.
PCI Express implements split transactions (transactions with request
and response separated by time), allowing the link to carry other
traffic while the target device gathers data for the response.
PCI Express uses credit-based flow control. In this scheme, a device
advertises an initial amount of credit for each received buffer in its
transaction layer. The device at the opposite end of the link, when
sending transactions to this device, counts the number of credits each
TLP consumes from its account. The sending device may only transmit a
TLP when doing so does not make its consumed credit count exceed its
credit limit. When the receiving device finishes processing the TLP
from its buffer, it signals a return of credits to the sending device,
which increases the credit limit by the restored amount. The credit
counters are modular counters, and the comparison of consumed credits
to credit limit requires modular arithmetic. The advantage of this
scheme (compared to other methods such as wait states or
handshake-based transfer protocols) is that the latency of credit
return does not affect performance, provided that the credit limit is
not encountered. This assumption is generally met if each device is
designed with adequate buffer sizes.
PCIe 1.x is often quoted to support a data rate of 250 MB/s in
each direction, per lane. This figure is a calculation from the
physical signaling rate (2.5 gigabaud) divided by the encoding
overhead (10 bits per byte.) This means a sixteen lane (×16) PCIe
card would then be theoretically capable of 16×250 MB/s =
4 GB/s in each direction. While this is correct in terms of data
bytes, more meaningful calculations are based on the usable data
payload rate, which depends on the profile of the traffic, which is a
function of the high-level (software) application and intermediate
Like other high data rate serial interconnect systems, PCIe has a
protocol and processing overhead due to the additional transfer
robustness (CRC and acknowledgements). Long continuous unidirectional
transfers (such as those typical in high-performance storage
controllers) can approach >95% of PCIe's raw (lane) data rate.
These transfers also benefit the most from increased number of lanes
(×2, ×4, etc.) But in more typical applications (such as a
Ethernet controller), the traffic profile is characterized as short
data packets with frequent enforced acknowledgements. This type of
traffic reduces the efficiency of the link, due to overhead from
packet parsing and forced interrupts (either in the device's host
interface or the PC's CPU). Being a protocol for devices connected to
the same printed circuit board, it does not require the same tolerance
for transmission errors as a protocol for communication over longer
distances, and thus, this loss of efficiency is not particular to
Nvidia GeForce GTX 650 Ti, a
PCI Express 3.0 ×16 graphics card
Gigabit Ethernet NIC, a
PCI Express ×1 card
A Marvell-based SATA 3.0 controller, as a
PCI Express ×1 card
PCI Express operates in consumer, server, and industrial applications,
as a motherboard-level interconnect (to link motherboard-mounted
peripherals), a passive backplane interconnect and as an expansion
card interface for add-in boards.
In virtually all modern (as of 2012[update]) PCs, from consumer
laptops and desktops to enterprise data servers, the PCIe bus serves
as the primary motherboard-level interconnect, connecting the host
system-processor with both integrated-peripherals (surface-mounted
ICs) and add-on peripherals (expansion cards). In most of these
systems, the PCIe bus co-exists with one or more legacy PCI buses, for
backward compatibility with the large body of legacy PCI peripherals.
As of 2013[update]
PCI Express has replaced AGP as the default
interface for graphics cards on new systems. Almost all models of
graphics cards released since 2010 by AMD (ATI) and
Nvidia use PCI
Nvidia uses the high-bandwidth data transfer of PCIe for its
Scalable Link Interface
Scalable Link Interface (SLI) technology, which allows multiple
graphics cards of the same chipset and model number to run in tandem,
allowing increased performance. AMD has also developed a multi-GPU
system based on PCIe called CrossFire. AMD and
Nvidia have released
motherboard chipsets that support as many as four PCIe ×16 slots,
allowing tri-GPU and quad-GPU card configurations.
Theoretically, external PCIe could give a notebook the graphics power
of a desktop, by connecting a notebook with any PCIe desktop video
card (enclosed in its own external housing, with strong power supply
and cooling); possible with an
ExpressCard interface or a Thunderbolt
ExpressCard interface provides bit rates of
5 Gbit/s (0.5 GB/s throughput), whereas the Thunderbolt
interface provides bit rates of up to 40 Gbit/s (5 GB/s
In 2017 more fully featured external card hubs were introduced. An
example for this year, with a full-length PCIe x16 interface, is the
Razer Core .
In 2010 external card hubs were introduced that can connect to a
laptop or desktop through a PCI
ExpressCard slot. These hubs can
accept full-sized graphics cards. Examples include MSI GUS,
Village Instrument's ViDock, the
Asus XG Station, Bplus PE4H V3.2
adapter, as well as more improvised DIY devices. However such
solutions are limited by the size (often only x1) and version of the
available PCIe slot on a laptop.
In 2008, AMD announced the
ATI XGP technology, based on a proprietary
cabling system that is compatible with PCIe ×8 signal
transmissions. This connector is available on the Fujitsu Amilo
and the Acer Ferrari One notebooks. Fujitsu launched their AMILO
GraphicBooster enclosure for XGP soon thereafter. Around 2010 Acer
launched the Dynavivid graphics dock for XGP.
Intel Thunderbolt interface has given opportunity to new and faster
products to connect with a PCIe card externally. Magma has released
the ExpressBox 3T, which can hold up to three PCIe cards (two at ×8
and one at ×4). MSI also released the Thunderbolt GUS II, a PCIe
chassis dedicated for video cards. Other products such as the
Sonnet’s Echo Express and mLogic’s mLink are Thunderbolt PCIe
chassis in a smaller form factor. However, all these products
require a computer with a Thunderbolt port (i.e., Thunderbolt
devices), such as Apple's
MacBook Pro models released in late 2013.
For the professional market,
Nvidia has developed the Quadro Plex
external PCIe family of GPUs that can be used for advanced graphic
applications. These video cards require a
PCI Express ×8 or ×16 slot
for the host-side card which connects to the Plex via a
eight PCIe lanes.
OCZ RevoDrive SSD, a full-height ×4
PCI Express card
SATA Express and NVM Express
PCI Express protocol can be used as data interface to flash memory
devices, such as memory cards and solid-state drives (SSDs).
XQD card is a memory card format utilizing PCI Express, developed by
the CompactFlash Association, with transfer rates of up to
Many high-performance, enterprise-class SSDs are designed as PCI
RAID controller cards with flash memory chips placed directly
on the circuit board, utilizing proprietary interfaces and custom
drivers to communicate with the operating system; this allows much
higher transfer rates (over 1 GB/s) and IOPS (over one million
I/O operations per second) when compared to
Serial ATA or SAS
drives. For example, in 2011
OCZ and Marvell co-developed a
PCI Express solid-state drive controller for a
PCI Express 3.0
×16 slot with maximum capacity of 12 TB and a performance of to
7.2 GB/s sequential transfers and up to 2.52 million IOPS in
SATA Express is an interface for connecting SSDs, by providing
PCI Express lanes as a pure
PCI Express connection to the
attached storage device.
M.2 is a specification for internally
mounted computer expansion cards and associated connectors, which also
PCI Express lanes.
PCI Express storage devices can implement both
AHCI logical interface
for backward compatibility, and
NVM Express logical interface for much
faster I/O operations provided by utilizing internal parallelism
offered by such devices. Enterprise-class SSDs can also implement SCSI
over PCI Express.
Certain data-center applications (such as large computer clusters)
require the use of fiber-optic interconnects due to the distance
limitations inherent in copper cabling. Typically, a network-oriented
standard such as
Fibre Channel suffices for these
applications, but in some cases the overhead introduced by routable
protocols is undesirable and a lower-level interconnect, such as
InfiniBand, RapidIO, or
NUMAlink is needed. Local-bus standards such
as PCIe and
HyperTransport can in principle be used for this
purpose, but as of 2015[update] solutions are only available from
niche vendors such as Dolphin ICS.
Other communications standards based on high bandwidth serial
architectures include InfiniBand, RapidIO, HyperTransport, Intel
QuickPath Interconnect, and the Mobile Industry Processor Interface
(MIPI). The differences are based on the trade-offs between
flexibility and extensibility vs latency and overhead. For example,
adding complex header information to a transmitted packet allows for
complex routing (
PCI Express is capable of this through an optional
End-to-End TLP Prefix feature). The additional overhead reduces
the effective bandwidth of the interface and complicates bus discovery
and initialization software. Also making the system hot-pluggable
requires that software track network topology changes.
such a technology.
Another example is making the packets shorter to decrease latency (as
is required if a bus must operate as a memory interface). Smaller
packets mean packet headers consume a higher percentage of the packet,
thus decreasing the effective bandwidth. Examples of bus protocols
designed for this purpose are
RapidIO and HyperTransport.
PCI Express falls somewhere in the middle, targeted by design as a
system interconnect (local bus) rather than a device interconnect or
routed network protocol. Additionally, its design goal of software
transparency constrains the protocol and raises its latency somewhat.
Delays in PCIe 4.0 implementations led to the
Gen-Z consortium, the
CCIX effort and an open Coherent Accelerator Processor Interface
(CAPI) all being announced by the end of 2016.
Active State Power Management (ASPM)
PCI configuration space
Serial Digital Video Out (SDVO)
List of device bit rates § Main buses
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Technical and de facto standards for wired computer buses
Network on a chip
Plug and play
List of bus bandwidths
Europe Card Bus
HP Precision Bus
HP GSC bus
PCI Extended (PCI-X)
PCI Express (PCIe)
Direct Media Interface (DMI)
Intel QuickPath Interconnect
Intel UltraPath Interconnect
Parallel ATA (PATA)
Serial ATA (SATA)
PCI Express (via
AHCI or NVMe logical device interface)
Apple Desktop Bus
IEEE-1284 (parallel port)
IEEE 1394 (FireWire)
Intel HD Audio
Interfaces are listed by their speed in the (roughly) ascending order,
so the interface at the end of each section should be the fastest.
Basic computer components
Refreshable braille display
Refreshable braille display
USB flash drive
Central processing unit
Central processing unit (CPU)
HDD / SSD / SSHD
Network interface controller
Random-access memory (RAM)
FireWire (IEEE 1394)
HDMI / DVI / VG