Because the NAND function has functional completeness all logic systems can be converted into NAND gates. This is also true for NOR gates. In principle, any combinatorial logic function can be realized with enough NAND gates. Contents 1 NAND 2 Making other gates by using NAND gates 2.1 NOT 2.2 AND 2.3 OR 2.4 NOR 2.5 XOR 2.6 XNOR 3 MUX 4 DEMUX 5 See also 6 External links 7 References NAND[edit]
A
Q = NOT( A AND B ) Truth Table Input A Input B Output Q 0 0 1 0 1 1 1 0 1 1 1 0 Making other gates by using NAND gates[edit]
A
Desired NOT Gate NAND Construction Q = NOT( A ) = A NAND A Truth Table Input A Output Q 0 1 1 0 AND[edit]
An
Desired AND Gate NAND Construction Q = A AND B = ( A NAND B ) NAND ( A NAND B ) Truth Table Input A Input B Output Q 0 0 0 0 1 0 1 0 0 1 1 1 OR[edit]
If the truth table for a
Desired OR Gate NAND Construction Q = A OR B = ( A NAND A ) NAND ( B NAND B ) Truth Table Input A Input B Output Q 0 0 0 0 1 1 1 0 1 1 1 1 NOR[edit]
A N
Desired NOR Gate NAND Construction Q = A NOR B = [ ( A NAND A ) NAND ( B NAND B ) ] NAND [ ( A NAND A ) NAND ( B NAND B ) ] Truth Table Input A Input B Output Q 0 0 1 0 1 0 1 0 0 1 1 0 XOR[edit]
An X
Desired XOR Gate NAND Construction Q = A XOR B = [ A NAND ( A NAND B ) ] NAND [ B NAND ( A NAND B ) ] Truth Table Input A Input B Output Q 0 0 0 0 1 1 1 0 1 1 1 0 Alternatively, the B-input of the XN
Desired Gate NAND Construction Q = A XOR B = [ B NAND ( A NAND A ) ] NAND [ A NAND ( B NAND B ) ] XNOR[edit]
An XN
Desired XNOR Gate NAND Construction Q = A XNOR B = [ ( A NAND A ) NAND ( B NAND B ) ] NAND ( A NAND B ) Truth Table Input A Input B Output Q 0 0 1 0 1 0 1 0 0 1 1 1 Alternatively, the 4-gate version of the X
Desired Gate NAND Construction Q = A XNOR B = [ A NAND ( A NAND B ) ] NAND [ B NAND ( A NAND B ) ] NAND [ A NAND ( A NAND B ) ] NAND [ B NAND ( A NAND B ) ] MUX[edit] A multiplexer or a MUX gate is a three-input gate that uses one of the inputs, called "selection bits", to select and output one of the other two inputs, called "data bits".[1] Desired MUX Gate NAND Construction Q = [A AND NOT (S)] OR (B AND S) = NOT NOT[ A AND NOT( S AND S ) ] AND NOT( B AND S ) Truth Table A B Select Output 0 0 0 0 0 1 0 0 1 0 0 1 1 1 0 1 0 0 1 0 0 1 1 1 1 0 1 0 1 1 1 1 DEMUX[edit] A demultiplexer performs the opposite function of a multiplexer: It takes a single input and channels it to one of two possible outputs according to a selector bit that specifies which output to choose.[1] Desired DEMUX Gate NAND Construction Truth Table Input Select A B 0 0 0 0 0 1 0 0 1 0 1 0 1 1 0 1 See also[edit] NOR logic. Like NAND gates, NOR gates are also universal gates. Functional Completeness External links[edit] TTL NAND and AND gates - All About Circuits Steps to Derive XOR from NAND gate. NAND Gate, Demonstrate an interactive simulation of the NAND Gate circuit created with Teahlab's simulator. References[edit] ^ a b Nisan, N. & Schocken, S., 2005. In: From NAND to Tetris: Building a Modern Computer from First Principles. s.l.:The MIT Press, p. 20. Available at: http://www.nand2tetris.org/chapters/chapter%2001.pdf Lancaster, Don (1974). TTL Cookbook (1st ed.). Indianapolis, IN: Howard W Sams. pp. 126–135. ISBN 0- |