MIPS (an acronym for
Contents 1 MIPS I 1.1 Registers 1.2 Instruction formats 1.3 CPU instructions 1.3.1 Loads and stores 1.3.2 ALU 1.3.3 Shifts 1.3.4 Multiplication and division 1.3.5 Jump and branch 1.3.6 Exception 1.4 FPU instructions 1.4.1 Arithmetic 1.4.2 Data transfer 1.4.3 Branch 2 MIPS II 3 MIPS III 4 MIPS IV 5 MIPS V 6 MIPS32/MIPS64 6.1 MIPS32/MIPS64 Release 1 6.2 MIPS32/MIPS64 Release 2 6.3 MIPS32/MIPS64 Release 3 6.4 MIPS32/MIPS64 Release 5 6.5 MIPS32/MIPS64 Release 6 7 microMIPS 8 Application-specific extensions 8.1 MIPS MCU 8.2 MIPS16 8.2.1 MIPS16e 8.2.2 MIPS16e2 8.3 MIPS DSP
8.4 MIPS
9 Simulators 10 See also 11 References 12 Further reading 13 External links MIPS I[edit]
The first version of the
Type -31- format (bits) -0- R opcode (6) rs (5) rt (5) rd (5) shamt (5) funct (6) I opcode (6) rs (5) rt (5) immediate (16) J opcode (6) address (26) CPU instructions[edit]
Loads and stores[edit]
MIPS I has instructions that load and store
Instruction name Mnemonic Format Encoding Load Byte LB I 3210 rs rt offset Load Halfword LH I 3310 rs rt offset Load Word Left LWL I 3410 rs rt offset Load Word LW I 3510 rs rt offset Load Byte Unsigned LBU I 3610 rs rt offset Load Halfword Unsigned LHU I 3710 rs rt offset Load Word Right LWR I 3810 rs rt offset Store Byte SB I 4010 rs rt offset Store Halfword SH I 4110 rs rt offset Store Word Left SWL I 4210 rs rt offset Store Word SW I 4310 rs rt offset Store Word Right SWR I 4610 rs rt offset ALU[edit]
MIPS I has instructions to perform addition and subtraction. These
instructions source their operands from two GPRs (rs and rt), and
write the result to a third GPR (rd). Alternatively, addition can
source one of the operands from a
Instruction name Mnemonic Format Encoding Add ADD R 010 rs rt rd 010 3210 Add Unsigned ADDU R 010 rs rt rd 010 3310 Subtract SUB R 010 rs rt rd 010 3410 Subtract Unsigned SUBU R 010 rs rt rd 010 3510 And AND R 010 rs rt rd 010 3610 Or OR R 010 rs rt rd 010 3710 Exclusive Or XOR R 010 rs rt rd 010 3810 Nor NOR R 010 rs rt rd 010 3910 Set on Less Than SLT R 010 rs rt rd 010 4210 Set on Less Than Unsigned SLTU R 010 rs rt rd 010 4310 Add Immediate ADDI I 810 rs rd immediate Add Immediate Unsigned ADDIU I 910 $s $d immediate Set on Less Than Immediate SLTI I 1010 $s $d immediate Set on Less Than Immediate Unsigned SLTIU I 1110 $s $d immediate And Immediate ANDI I 1210 $s $d immediate Or Immediate ORI I 1310 $s $d immediate Exclusive Or Immediate XORI I 1410 $s $d immediate Load Upper Immediate LUI I 1510 010 $d immediate Shifts[edit] MIPS I has instructions to perform left and right logical shifts and right arithmetic shifts. The operand is obtained from a GPR (rt), and the result is written to another GPR (rd). The shift distance is obtained from either a GPR (rs) or a 5-bit "shift amount" (the "sa" field). Instruction name Mnemonic Format Encoding Shift Left Logical SLL R 010 010 rt rd ra 010 Shift Right Logical SRL R 010 010 rt rd sa 210 Shift Right Arithmetic SRA R 010 010 rt rd sa 310 Shift Left Logical Variable SLLV R 010 rs rt rd 010 410 Shift Right Logical Variable SRLV R 010 rs rt rd 010 610 Shift Right Arithmetic Variable SRAV R 010 rs rt rd 010 710 Multiplication and division[edit]
MIPS I has instructions for signed and unsigned integer multiplication
and division. These instructions source their operands from two GPRs
and write their results to a pair of
Instruction name Mnemonic Format Encoding Move from HI MFHI R 010 010 010 rd 010 1610 Move to HI MTHI R 010 rs 010 010 010 1710 Move from LO MFLO R 010 010 010 rd 010 1810 Move to LO MTLO R 010 rs 010 010 010 1910 Multiply MULT R 010 rs rt 010 010 2410 Multiply Unsigned MULTU R 010 rs rt 010 010 2510 Divide DIV R 010 rs rt 010 010 2610 Divide Unsigned DIVU R 010 rs rt 010 010 2710 Jump and branch[edit]
All MIPS I control flow instructions are followed by a branch delay
slot. Unless the branch delay slot is filled by an instruction
performing useful work, an nop is substituted. MIPS I branch
instructions compare the contents of a GPR (rs) against zero or
another GPR (rt) as signed integers and branch if the specified
condition is true. Control is transferred to the address computed by
shifting the
Instruction name Mnemonic Format Encoding Jump Register JR R 010 rs 010 010 010 810 Jump and Link Register JALR R 010 rs 010 rd 010 910 Branch on Less Than Zero BLTZ I 110 rs 010 offset Branch on Greater Than or Equal to Zero BGEZ I 110 rs 110 offset Branch on Less Than Zero and Link BLTZAL I 110 rs 16 offset Branch on Greater Than or Equal to Zero and Link BGEZAL I 110 rs 17 offset Jump J J 210 instr_index Jump and Link JAL J 310 instr_index Branch on Equal BEQ I 410 rs rt offset Branch on Not Equal BNE I 510 rs rt offset Branch on Less Than or Equal to Zero BLEZ I 610 rs 010 offset Branch on Greater Than Zero BGTZ I 710 rs 010 offset Exception[edit] MIPS I has two instructions for software to signal an exception: System Call and Breakpoint. System Call is used by user mode software to make kernel calls; and Breakpoint is used to transfer control to a debugger via the kernel's exception handler. Both instructions have a 20-bit Code field that can contain operating environment-specific information for the exception handler. Instruction name Mnemonic Format Encoding System Call SYSCALL ? 010 Code 1210 Breakpoint BREAK ? 010 Code 1310 FPU instructions[edit] MIPS has 32 floating-point registers. Two registers are paired for double precision numbers. Odd numbered registers cannot be used for arithmetic or branching, just as part of a double precision register pair, resulting in 16 usable registers for most instructions (moves/copies and loads/stores were not affected). Arithmetic[edit] Name Instruction syntax Meaning opcode rs rt rd sham funct Floating-Point Add add.s $x,$y,$z $x = $y + $z 1710 010 $z $y $x 010 Floating-Point Subtract sub.s $x,$y,$z $x = $y - $z 1710 010 $z $y $x 110 Floating-Point Multiply mul.s $x,$y,$z $x = $y * $z 1710 010 $z $y $x 210 Floating-Point Divide div.s $x,$y,$z $x = $y / $z 1710 010 $z $y $x 310 Floating-Point Add add.d $x,$y,$z $x = $y + $z 1710 110 $z $y $x 010 Floating-Point Subtract sub.d $x,$y,$z $x = $y - $z 1710 110 $z $y $x 110 Floating-Point Multiply mul.d $x,$y,$z $x = $y * $z 1710 110 $z $y $x 210 Floating-Point Divide div.d $x,$y,$z $x = $y / $z 1710 110 $z $y $x 310 Floating-Point Compare (eq,ne,lt,le,gt,ge) c.lt.s $f2,$f4 cond = ($f2 < $f4) Floating-Point Compare (eq,ne,lt,le,gt,ge) c.lt.d $f2,$f4 cond = ($f2 < $f4) Single precision is denoted by the .s suffix, while double precision is denoted by the .d suffix. Data transfer[edit] Name Instruction syntax Meaning Format opcode funct Notes/Encoding Load word coprocessor lwcZ $x,CONST ($y) Coprocessor[Z].DataRegister[$x] = Memory[$y + CONST] I Loads the 4 byte word stored from: MEM[$y+CONST] into a Coprocessor data register. Sign extension. Store word coprocessor swcZ $x,CONST ($y) Memory[$y + CONST] = Coprocessor[Z].DataRegister[$x] I Stores the 4 byte word held by a
Branch[edit] Name Instruction syntax Meaning Format opcode funct Notes/Encoding Branch on FP True bc1t 100 if (cond) goto PC+4+100; PC relative branch if FP condition Branch on FP False bc1f 100 if (!cond) goto PC+4+100; PC relative branch if not condition MIPS II[edit]
Instructions added to MIPS II[1] Name Mnemonic Synchronize Shared Memory SYNC Trap if Greater Than or Equal TGE Trap if Greater Than or Equal Unsigned TGEU Trap if Less Than TLT Trap if Less Than Unsigned TLTU Trap if Equal TEQ Trap if Not Equal TNE Branch on Less Than or Equal to Zero Likely BLEZL Branch on Greater Than or Equal to Zero Likely BGEZL Trap if Greater Than or Equal Immediate TGEI Trap if Greater Than or Equal Unsigned Immediate TGEIU Trap if Less Than Immediate TLTI Trap if Less Than Unsigned Immediate TLTIU Trap if Equal Immediate TEQI Trap if Not Equal Immediate TNEI Branch on Less Than Zero and Link Likely BLTZALL Branch on Greater Than or Equal to Zero and Link Likely BGEZAL Floating-Point Square Root SQRT.S Floating-Point Square Root SQRT.D Floating-Point Round to Word Fixed-Point ROUND.S Floating-Point Round to Word Fixed-Point ROUND.D Floating-Point Truncate to Word Fixed-Point TRUNC.S Floating-Point Truncate to Word Fixed-Point TRUNC.D Floating-Point Ceiling to Word Fixed-Point CEIL.S Floating-Point Ceiling to Word Fixed-Point CEIL.D Floating-Point Ceiling to Word Fixed-Point FLOOR.S Floating-Point Ceiling to Word Fixed-Point FLOOR.D Branch on FP False Likely BC1FL Branch on FP True Likely BC1TL Branch on Equal Likely BEQL Branch on Not Equal Likely BNEL Branch on Less Than Zero Likely BLTZL Branch on Greater Than Zero Likely BGTZL Load Linked LL Load Doubleword to
Load Doubleword to
Load Doubleword to
Store Conditional SC Store Doubleword to
Store Doubleword to
Store Doubleword to
MIPS III[edit]
CPU instructions added by MIPS III Instruction name Mnemonic Format Encoding Doubleword Shift Left Logical Variable DSLLV R 0 rs rt rd 0 20 Doubleword Shift Right Logical Variable DSRLV R 0 rs rt rd 0 22 Doubleword Shift Right Arithmetic Variable DSRAV R 0 rs rt rd 0 23 Doubleword Multiply DMULT R 0 rs rt 0 0 28 Doubleword Multiply Unsigned DMULTU R 0 rs rt 0 0 29 Doubleword Divide DDIV R 0 rs rt 0 0 30 Doubleword Divide Unsigned DDIVU R 0 rs rt 0 0 31 Doubleword Add DADD R 0 rs rt rd 0 44 Doubleword Add Unsigned DADDU R 0 rs rt rd 0 45 Doubleword Subtract DSUB R 0 rs rt rd 0 46 Doubleword Subtract Unsigned DSUBU R 0 rs rt rd 0 47 Doubleword Shift Left Logical DSLL R 0 0 rt rd sa 56 Doubleword Shift Right Logical DSRL R 0 0 rt rd sa 58 Doubleword Shift Right Arithmetic DSRA R 0 0 rt rd sa 59 Doubleword Shift Left Logical + 32 DSLL32 R 0 0 rt rd sa 60 Doubleword Shift Right Logical + 32 DSRL32 R 0 0 rt rd sa 62 Doubleword Shift Right Logical + 32 DSRL32 R 0 0 rt rd sa 63 Doubleword Add Immediate DADDI I 24 rs rd immediate Doubleword Add Immediate Unsigned DADDIU I 25 rs rd immediate Load Doubleword Left LDL I 26 rs rt offset Load Doubleword Right LDR I 27 rs rt offset Load Word Unsigned LWU I 39 rs rt offset Store Doubleword Left SDL I 44 rs rt offset Store Doubleword Right SDR I 45 rs rt offset Load-Linked Doubleword LLD I 52 rs rt offset Load Doubleword LD I 55 rs rt offset Store-Conditional Doubleword SCD I 60 rs rt offset Store Doubleword SD I 64 rs rt offset
FPU instructions added by MIPS III Instruction name Mnemonic Format Encoding Doubleword Move To
Doubleword Move To
Floating Point Round to Long ROUND.L.S R 17 16 0 fs fd 8 Floating Point Round to Long ROUND.L.D R 17 17 0 fs fd 8 Floating Point Truncate to Long TRUNC.L.S R 17 16 0 fs fd 9 Floating Point Truncate to Long TRUNC.L.D R 17 17 0 fs fd 9 Floating Point Ceiling to Long CEIL.L.S R 17 16 0 fs fd 10 Floating Point Ceiling to Long CEIL.L.D R 17 17 0 fs fd 10 Floating Point Floor to Long FLOOR.L.S R 17 16 0 fs fd 11 Floating Point Floor to Long FLOOR.L.D R 17 17 0 fs fd 11 Floating Point Convert to Single CVT.S.L R 17 16 0 fs fd 32 Floating Point Convert to Double CVT.D.L R 17 17 0 fs fd 33 Floating Point Convert to Long CVT.L.S R 17 16 0 fs fd 37 Floating Point Convert to Long CVT.L.D R 17 17 0 fs fd 37 MIPS Computer Systems'
a new family of branches with no delay slot: unconditional branches (BC) & branch-and-link (BALC) with a 26-bit offset, conditional branch on zero/non-zero with a 21-bit offset, full set of signed & unsigned conditional branches compare between two registers (e.g. BGTUC) or a register against zero (e.g. BGTZC), full set of branch-and-link which compare a register against zero (e.g. BGTZALC). index jump instructions with no delay slot designed to support large
absolute addresses.
instructions to load
Removed infrequently used instructions: some conditional moves
branch likely instructions (deprecated in previous releases).
integer overflow trapping instructions with
Reorganized the instruction encoding, freeing space for future
expansions.
microMIPS[edit]
The microMIPS32/64 architectures are supersets of the MIPS32 and
MIPS64 architectures (respectively) designed to replace the MIPS16e
ASE. A disadvantage of MIPS16e is that it requires a mode switch
before any of its
Separate priority and vector generation
Supports up to 256 interrupts in EIC (External Interrupt Controller)
mode and eight hardware interrupt pins
Provides
MIPS16[edit]
MIPS16 is an Application-Specific Extension for MIPS I through to V
designed by
Saturating arithmetic (when a calculation overflows, deliver the
representable number closest to the non-overflowed answer).
Fixed-point arithmetic on signed 32- and
To make use of MIPS DSP ASE, you may: Hand-code in assembly language, which is the most time-consuming
method of utilizing the MIPS DSP ASE, but can produce code with the
highest performance.
Use asm macros supported by GCC that produce DSP instructions directly
from C code.
Use intrinsics supported by GCC for the MIPS DSP ASE.
Use fixed-point data types and operators in C supported by GCC. The
MIPS DSP ASE is the only processor architecture that supports
fixed-point data types in a general-purpose processor.
Use auto-vectorization supported by GCC for loops via the optimization
option -ftree-vectorize. The advantage of auto-vectorization is that
the compiler can recognize scalar variables (which can be integer,
fixed-point, or floating-point types) in order to utilize SIMD
instructions automatically. In the ideal case, when auto-vectorization
is used, there is no need to use
Linux 2.6.12-rc5 starting 2005-05-31 adds support for the DSP
ASE. Note that to actually make use of the DSP ASE a toolchain which
support this is required. GCC already has support for DSP and DSPr2.
MIPS
32 vector registers of 16 x 8-bit, 8 x 16-bit, 4 x 32-bit, and 2 x 64 bit vector elements Efficient vector parallel arithmetic operations on integer, fixed-point and floating-point data Operations on absolute value operands Rounding and saturation options available Full precision multiply and multiply-add Conversions between integer, floating-point, and fixed-point data Complete set of vector-level compare and branch instructions with no condition flag Vector (1D) and array (2D) shuffle operations Typed load and store instructions for endian-independent operation IEEE Standard for Floating-Point Arithmetic 754-2008 compliant Element precise floating-point exception signaling Pre-defined scalable extensions for chips with more gates/transistors Accelerates compute-intensive applications in conjunction with leveraging generic compiler support Software-programmable solution for consumer electronics applications or functions not covered by dedicated hardware Emerging data mining, feature extraction, image and video processing, and human-computer interaction applications High-performance scientific computing MIPS virtualization[edit]
Hardware supported virtualization technology.
MIPS multi-threading[edit]
Each multi-threaded MIPS core can support up to two VPEs (Virtual
Processing Elements) which share a single pipeline as well as other
hardware resources. However, since each VPE includes a complete copy
of the processor state as seen by the software system, each VPE
appears as a complete standalone processor to an SMP Linux operating
system. For more fine-grained thread processing applications, each VPE
is capable of supporting up to nine TCs allocated across two VPEs. The
TCs share a common execution unit but each has its own program counter
and core register files so that each can handle a thread from the
software. The MIPS MT architecture also allows the allocation of
processor cycles to threads, and sets the relative thread priorities
with an optional Quality of Service (QoS) manager block. This enables
two prioritization mechanisms that determine the flow of information
across the bus. The first mechanism allows the user to prioritize one
thread over another. The second mechanism is used to allocate a
specified ratio of the cycles to specific threads over time. The
combined use of both mechanisms allows effective allocation of
bandwidth to the set of threads, and better control of latencies. In
real-time systems, system-level determinism is very critical, and the
QoS block facilitates improvement of the predictability of a system.
Hardware designers of advanced systems may replace the standard QoS
block provided by
DLX, a very similar architecture designed by
References[edit] ^ a b c Price, Charles (September 1995).
Further reading[edit] Farquhar, Erin; Philip Bunce. MIPS Programmer's Handbook. Morgan Kaufmann Publishers. ISBN 1-55860-297-6. Patterson, David A; John L. Hennessy. Computer Organization and Design: The Hardware/Software Interface. Morgan Kaufmann Publishers. ISBN 1-55860-604-1. Sweetman, Dominic. See MIPS Run. Morgan Kaufmann Publishers. ISBN 1-55860-410-3. Sweetman, Dominic. See MIPS Run, 2nd edition. Morgan Kaufmann Publishers. ISBN 0-12-088421-6. External links[edit] Wikibooks has a book on the topic of: MIPS Assembly MIPS Processors prpl Foundation (a non-profit foundation founded by Imagination Technologies to support the MIPS platform) MIPS Architecture history diagram Online MIPS emulator MIPS Instuctions - MIPS Instruction Set v t e MIPS microprocessors MIPS architecture
Application Processors MIPS32 compatible Ingenic XBurst JZ4720 Ben NanoNote JZ4730 (Skytone Alpha-400) JZ4740 (Dingoo A320) JZ4750 (Game Gadget) JZ4760 Velocity Micro T103 Cruz Velocity Micro T301 Cruz JZ4770 Ainol Novo7 Paladin NEOGEO-X GCW-Zero JZ4780 Microcontrollers M4K
4Kc/4KEc ATI/AMD/
Networking 4Kc/4KEc Qualcomm Atheros AR2313 AR2318 MediaTek RT2880 Texas Instruments/Infineon/Lantiq AR7 Lantiq AMAZON 24Kc/24KEc Qualcomm Atheros AR7240 AR7161 AR9132 AR9331 MediaTek RT3050 RT3350 RT5350 RT6856 Lantiq DANUBE VINAX 34Kc Lantiq AR188 VRX288 GRX388 Ikanos Fusiv Vx175/173 Fusiv Vx180 Fusiv Vx185/183 74Kc Qualcomm Atheros AR9344 QCA9558 MediaTek RT3662 RT3883 Broadcom BCM4706 MIPS32 compatible Broadcom various Cavium various Alchemy Semiconductor Alchemy RMI Corporation XLR 5Kc Marvell 88E6318 "Link Street" MIPS64 compatible Broadcom various Cavium Octeon Gaming various
Supercomputer Loongson SiCortex Classic Processors MIPS I R2000 R3000 MIPS II R6000 MIPS III R4000 R4400 R4200 R4300i R4600 R4700 MIPS IV R5000 R8000 R10000 R12000 R12000A R14000 R14000A R16000 R16000A R18000 MIPS V v t e
Berkeley RISC IBM 801 Stanford MIPS Active Altera Nios II Analog Devices Blackfin ARC ARM Atmel AVR DLX eSi-RISC LatticeMico8 LatticeMico32 Meta MIPS OpenRISC Power POWER PowerPC Cell Renesas M32R Renesas SuperH Renesas V850 RISC-V S+core Sunway SPARC Unicore Xilinx MicroBlaze Xilinx PicoBlaze XMOS XCore XS1 VISC Mill Historic Alpha AMD Am29000 Apollo PRISM Atmel AVR32 Clipper CRISP DEC Prism Intel i860 Intel i960 MIPS-X Motorola 88000 PA-RISC ROMP v t e CPU technologies Architecture Turing machine Post–Turing machine Universal Turing machine Quantum Turing machine Belt machine Stack machine Register machine Counter machine Pointer machine Random access machine Random access stored program machine Finite-state machine Queue automaton Von Neumann Harvard (modified) Dataflow TTA Cellular Artificial neural network Machine learning Deep learning Neural processing unit (NPU) Convolutional neural network
Load/store architecture
Register memory architecture
Endianness
FIFO
Zero-copy
NUMA
HUMA
HSA
Mobile computing
Surface computing
Wearable computing
Heterogeneous computing
Parallel computing
Concurrent computing
Distributed computing
Cloud computing
Amorphous computing
Ubiquitous computing
Fabric computing
Cognitive computing
Unconventional computing
Hypercomputation
Quantum computing
Adiabatic quantum computing
Linear optical quantum computing
Reversible computing
Reverse computation
Reconfigurable computing
Optical computing
Ternary computer
Analogous computing
Mechanical computing
Hybrid computing
Digital computing
DNA computing
Peptide computing
Chemical computing
Organic computing
Wetware computing
Neuromorphic computing
ISA types ASIP CISC RISC EDGE (TRIPS) VLIW (EPIC) MISC OISC NISC ZISC Comparison ISAs x86
z/Architecture
ARM
MIPS
Word size 1-bit 2-bit 4-bit 8-bit 9-bit 10-bit 12-bit 15-bit 16-bit 18-bit 22-bit 24-bit 25-bit 26-bit 27-bit 31-bit 32-bit 33-bit 34-bit 36-bit 39-bit 40-bit 48-bit 50-bit 60-bit 64-bit 128-bit 256-bit 512-bit Variable Execution Instruction pipelining Bubble Operand forwarding Out-of-order execution Register renaming Speculative execution Branch predictor Memory dependence prediction Hazards Parallel level Bit Bit-serial Word Instruction Pipelining Scalar Superscalar Task Thread Process Data Vector Memory Multithreading Temporal Simultaneous (SMT) (Hyper-threading) Speculative (SpMT) Preemptive Cooperative Clustered Multi-Thread (CMT) Hardware scout Flynn's taxonomy SISD
SPMD Addressing mode CPU performance
Core count
Types
Components
Combinational logic
Sequential logic
Quantum gate Gate array Counter (digital) Bus (computing) Semiconductor device Clock rate CPU multiplier Vision chip Memristor Power management APM ACPI Dynamic frequency scaling Dynamic voltage scaling Clock gating Hardware security Non-executable memory (NX bit)
Memory Protection Extensions (Intel MPX)
Intel Secure Key
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