In computer architecture, a processor register is a quickly accessible
location available to a computer's central processing unit (CPU).
Registers usually consist of a small amount of fast storage, although
some registers have specific hardware functions, and may be read-only
or write-only. Registers are typically addressed by mechanisms other
than main memory, but may in some cases be assigned a memory address
e.g. DEC PDP-10, ICT 1900.
Almost all computers, whether load/store architecture or not, load
data from a larger memory into registers where it is used for
arithmetic operations and is manipulated or tested by machine
instructions. Manipulated data is then often stored back to main
memory, either by the same instruction or by a subsequent one. Modern
processors use either static or dynamic RAM as main memory, with the
latter usually accessed via one or more cache levels.
Processor registers are normally at the top of the memory hierarchy,
and provide the fastest way to access data. The term normally refers
only to the group of registers that are directly encoded as part of an
instruction, as defined by the instruction set. However, modern
high-performance CPUs often have duplicates of these "architectural
registers" in order to improve performance via register renaming,
allowing parallel and speculative execution. Modern x86 design
acquired these techniques around 1995 with the releases of Pentium
1 Categories of registers 2 Examples 3 Register usage 4 See also 5 References
Categories of registers
Registers are normally measured by the number of bits they can hold,
for example, an "
8-bit register" or a "
User-accessible registers can be read or written by machine instructions. The most common division of user-accessible registers is into data registers and address registers.
Data registers can hold numeric data values such as integer and, in some architectures, floating-point values, as well as characters, small bit arrays and other data. In some older and low end CPUs, a special data register, known as the accumulator, is used implicitly for many operations. Address registers hold addresses and are used by instructions that indirectly access primary memory.
Some processors contain registers that may only be used to hold an address or only to hold numeric values (in some cases used as an index register whose value is added as an offset from some address); others allow registers to hold either kind of quantity. A wide variety of possible addressing modes, used to specify the effective address of an operand, exist. The stack pointer is used to manage the run-time stack. Rarely, other data stacks are addressed by dedicated address registers, see stack machine.
General-purpose registers (GPRs) can store both data and addresses, i.e., they are combined data/address registers and rarely the register file is unified to include floating point as well. Status registers hold truth values often used to determine whether some instruction should or should not be executed. Floating-point registers (FPRs) store floating point numbers in many architectures. Constant registers hold read-only values such as zero, one, or pi. Vector registers hold data for vector processing done by SIMD instructions (Single Instruction, Multiple Data). Special-purpose registers (SPRs) hold program state; they usually include the program counter, also called the instruction pointer, and the status register; the program counter and status register might be combined in a program status word (PSW) register. The aforementioned stack pointer is sometimes also included in this group. Embedded microprocessors can also have registers corresponding to specialized hardware elements. In some architectures, model-specific registers (also called machine-specific registers) store data and settings related to the processor itself. Because their meanings are attached to the design of a specific processor, they cannot be expected to remain standard between processor generations. Memory Type Range Registers (MTRRs)
Internal registers – registers not accessible by instructions, used internally for processor operations.
Instruction register, holding the instruction currently being executed. Registers related to fetching information from RAM, a collection of storage registers located on separate chips from the CPU:
Architectural register - The registers visible to software defined by an architecture may not correspond to the physical hardware, if there is register renaming being performed by underlying hardware.
Hardware registers are similar, but occur outside CPUs.
In some architectures (such as
Architecture GPRs/data+address registers FP registers Notes
stack of 7
The AT&T Hobbit ATT92010 (around 1992) was a commercial version of
Cray-1 8 scalar data, 8 address 8 scalar, 8 vector (64 elements) Scalar data registers can be integer or floating-point; also 64 scalar scratch-pad T registers and 64 address scratch-pad B registers
4004 1 accumulator, 16 others 0 Register A is for general purpose, while r0–r15 registers are for the address and segment.
8008 1 accumulator, 6 others 0 The A register is an accumulator to which all arithmetic is done; the H and L registers can be used in combination as an address register; all registers can be used as operands in load/store/move/increment/decrement instructions and as the other operand in arithmetic instructions. There is no FP unit available.
1 accumulator, 6 others
Plus a stack pointer. The A register is an accumulator to which all
arithmetic is done; the register pairs B+C, D+E, and H+L, can be used
as address registers in some instructions; all registers can be used
as operands in load/store/move/increment/decrement instructions and as
the other operand in arithmetic instructions. Some instructions only
use H+L; another instruction swaps H+L and D+E. Floating point
processors intended for the
stack of 6
The iAPX 432 was referred to as a micromainframe, designed to be
programmed entirely in high-level languages. The instruction set
architecture was also entirely new and a significant departure from
16-bit x86 8 stack of 8 (if FP present) 8086/8088, 80186/80188, 80286, with 8087, 80187 or 80287 for floating-point, with an 80-bit wide, 8 deep register stack with some instructions able to use registers relative to the top of the stack as operands; without 8087/80187/80287, no floating-point registers
stack of 8 (if FP present), 8 (if SSE/MMX present)
80386 required 80387 for floating-point, later processors had built-in
floating point, with both having an 80-bit wide, 8 deep register stack
with some instructions able to use registers relative to the top of
the stack as operands. The
Xeon Phi 16 32 Including 32 256/5 12-bit ZMM registers with AVX-512.
1 data, 1 address
Geode GX/Media GX/4x86/5x86 is the emulation of 486/Pentium compatible
processor made by Cyrix/National Semiconductor. Like Transmeta, the
processor had a translation layer that translated x86 code to native
code and executed it. It does not support 12
registers, just the 80387 stack of eight 80-bit floating point
registers, and partially support
3DNow! from AMD. The native processor
only contains 1 data and 1 address register for all purpose and
translated into 4 paths of
VM Labs Nuon
Nios II is based on MIPS IV instruction set and has
SH 16-bit 1 6
the Tesla 1.0-based G8x contains 8×12 8-bit HDR vector registers, the Tesla 2.0-based GT200 increased the count to 16×128-bit Fermi extended the register width to 256 bits and increased the register count to 32, (32×256-bit) Kepler increased it to 64. (64×256-bit) Maxwell contains a massive amount of 128 5 12-bit vector registers. (128×512-bit) Pascal: ? Volta: ?
4 (if FP present)
This applies to S/360's successors,
An instruction set designed by
NS320xx 8 8 (if FP present)
Xelerated X10 1 32 a 32/40 bit stack machine based network processor with modified MIPS instruction and 128 bit floating point unit.
Parallax Propeller 0 2 An eight core 8/16 bit sliced stack machine controller with simple logic circus inside, have eight cog counter(core) and each contain three 8/16 bit special control registers with 32 bit x 512 stack ram however it does not carrying any general register for integer purpose. unlike most of shadow register file in modern processor and multi core system, all these stack ram in cog can be accessed in instruction level which all these cog can act as one big single general purpose core if necessary. Floating point unit is external and it contain two 80 bit vector register.
Itanium 128 128 And 64 1-bit predicate registers and 8 branch registers. The FP registers are 82-bit.
SPARC 31 32 Global register 0 is hardwired to 0. Uses register windows.
IBM POWER 32 32 And 1 link and 1 count register.
Power Architecture 32 32 And 1 link and 1 count register. Processors supporting the Vector facility also have 32 12 8-bit vector registers,
Blackfin 8 16 containing two external uncore 40 bit accumulator, but non are general purpose. Support 64 bit RISC architecture ISA, vector register are 256 bit.
PDP-10 16 0 All may be used generally (integer, float, stack pointer, jump, indexing, etc.). Every 36-bit memory (or register) word can also be manipulated as a half-word, which can be considered an (18-bit) address. Other word interpretations are used by certain instructions. In the original PDP-10 processors, these 16 GPRs also corresponded to main (i.e. core) memory locations 0-15; a hardware option called "fast memory" implemented the registers as separate ICs, and references to memory locations 0-15 referred to the IC registers. Later models implemented the registers as "fast memory" and continued to make memory locations 0-15 refer to them. Movement instructions take (register, memory) operands: MOVE 1,2 is register-register, and MOVE 1,1000 is memory-to-register.
PDP-11 8 0 R7 is actually the Program Counter. Any register can be a stack pointer but R6 is used for hardware interrupts and traps.
VAX 16 0 Three of the registers have special uses: R12 (Argument Pointer), R13 (Frame Pointer), and R14 (Stack Pointer), while R15 refers to the Program Counter.
Alpha 31 31 Registers R31 (integer) and F31 (floating-point) are hardwired to zero.
6502 1 data, 2 index 0 6502's content A (Accumulator) register for main purpose data store and memory address ( 8-bit data/ 16-bit address), X,Y are indirect and direct index registers (respectively) and SP register are specific index only.
Direct successor of 6502, 65002 only content A (Accumulator) register
for main purpose data store and extend data wide to
PIC microcontroller 1 0
AVR microcontroller 32 0
MIPS 31 32 Register 0 is hardwired to 0.
Epiphany 64 (per core) Each instruction controls whether registers are interpreted as integers or single precision floating point. Architecture is scalable to 4096 cores with 16 and 64 core implementations currently available.
The number of registers available on a processor and the operations
that can be performed using those registers has a significant impact
on the efficiency of code generated by optimizing compilers. The
Computer science portal
CPU cache Register allocation Register file Shift register
^ a b "A Survey of Techniques for Designing and Managing CPU Register
File". Concurrency and Computation. Wiley. 2016.
^ "A Survey of Techniques for Architecting and Managing GPU Register
File", IEEE TPDS, 2016
^ "great microprocessor of the past and present". cpushock. April
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