FeiTeng (飞腾, fēiténg) is the name of several computer

central processing unit A central processing unit (CPU), also called a central processor, main processor or just Processor (computing), processor, is the electronic circuitry that executes Instruction (computing), instructions comprising a computer program. The CPU per ...

s designed and produced in China for supercomputing applications. The microprocessors have been developed by Tianjin Phytium Technology. The processors have also been described as the YinHeFeiTeng (银河飞騰, YHFT) family. This CPU family has been developed by a team directed by NUDT's Professor Xing Zuocheng.

Initial designs

The first generation was

binary compatible Binary-code compatibility (binary compatible or object-code-compatible) is a property of a computer system, meaning that it can run the same executable code, typically machine code for a general-purpose computer CPU, that another computer syste ...

with the Intel Itanium 2. The second generation, the FT64, was a system on a chip with CPU and 64-bit stream processor. FT64 chips were used in YinHe (银河) supercomputers as accelerators.

FeiTeng-1000

The FeiTeng-1000 is the third generation CPU in the family. It is manufactured with 65 nm technology and contains 350 million gates. Its clock frequency is 0.8–1 GHz. It is compatible with the SPARCv9 instruction set architecture. Each chip contains 8 cores and is capable of executing 64 threads. There are 3

HyperTransport HyperTransport (HT), formerly known as Lightning Data Transport, is a technology for interconnection of computer processors. It is a bidirectional serial/ parallel high-bandwidth, low- latency point-to-point link that was introduced on Apri ...

channels for coherent links, 4

DDR3 Double Data Rate 3 Synchronous Dynamic Random-Access Memory (DDR3 SDRAM) is a type of synchronous dynamic random-access memory (SDRAM) with a high bandwidth (" double data rate") interface, and has been in use since 2007. It is the higher-spee ...

memory controllers and a 8x PCIe 2.0 link. The

Tianhe-1A Tianhe-I, Tianhe-1, or TH-1 (, ; '' Sky River Number One'') is a supercomputer capable of an Rmax (maximum range) of 2.5 peta FLOPS. Located at the National Supercomputing Center of Tianjin, China, it was the fastest computer in the worl ...

supercomputer uses 2,048 FeiTeng 1000 processors. Tianhe-1A has a theoretical peak performance of 4.701 petaflops, also employing 7,168 Nvidia Tesla M2050 GPUs and 14,336 Intel Xeon X5670 CPUs in addition to FT1000 processors.''The TianHe-1A Supercomputer: Its Hardware and Software'' by Xue-Jun Yang, Xiang-Ke Liao, et al in the ''Journal of Computer Science and Technology'', Volume 26, Number 3, May 2011, pp. 344–351 The FeiTeng-1000 is an eight-core processor based on the

SPARC SPARC (Scalable Processor Architecture) is a reduced instruction set computer (RISC) instruction set architecture originally developed by Sun Microsystems. Its design was strongly influenced by the experimental Berkeley RISC system develope ...

system and is used to operate service nodes on the Tianhe-1. A 2012 report for the European High Performance Computing service stated that FeiTeng used the work of the

OpenSPARC OpenSPARC is an open-source hardware project started in December 2005. The initial contribution to the project was Sun Microsystems' register-transfer level (RTL) Verilog code for a full 64-bit, 32- thread microprocessor, the UltraSPARC T1 process ...

project.

Galaxy FT-1500

Tianhe-2 Tianhe-2 or TH-2 (, i.e. 'Milky Way 2') is a 33.86- petaflops supercomputer located in the National Supercomputer Center in Guangzhou, China. It was developed by a team of 1,300 scientists and engineers. It was the world's fastest supercomputer ...

supercomputer uses 4096 processors Galaxy FT-1500 with 16 cores,

architecture based and 65 W TDP. They are made with 40 nm technology, processor cores work at 1.8 GHz. Peak performance of FT-1500 is 115–144 GFLOPS; every core may execute up to 8 interleaving threads and supports 256-bit wide SIMD vector operations including Fused Mul-Add (FMA). Cache of this SoC works at 2 GHz frequency, there are 16 KB L1i, 16 KB L1d, 512 KB L2 per core, and shared 4 MB L3 cache. L3 cache has 4 segments (1 segment per block of 4 CPU cores), each of 1 MB with 32-way associative. Cache uses directory-based cache coherency protocol. FT-1500 also has: * Links to connect several processors into NUMA machine * 4 integrated DDR3 memory controllers * 2 PCI-express controllers * 10 Gbit Ethernet ports

FT-1500A

FT-1500A is an

ARM64 AArch64 or ARM64 is the 64-bit extension of the ARM architecture family. It was first introduced with the Armv8-A architecture. Arm releases a new extension every year. ARMv8.x and ARMv9.x extensions and features Announced in October 2011, AR ...

SoC designed by Phytium, which includes 16 cores of

ARMv8 ARM (stylised in lowercase as arm, formerly an acronym for Advanced RISC Machines and originally Acorn RISC Machine) is a family of reduced instruction set computer (RISC) instruction set architectures for computer processors, configured ...

processor, a 32-lane PCIe host, 2 GMAC on-chip ethernet controller and a GICv3 interrupt controller with ITS support.

Future processors

In 2020, Feiteng announced availability of the S2500 processor and a roadmap for the following years.

References