In digital electronic design a clock domain crossing (CDC), or simply
clock crossing, is the traversal of a signal in a
synchronous digital circuit from one
clock domain into another. If a signal does not assert
long enough and is not registered, it may appear
asynchronous on the incoming clock boundary.
A synchronous system is composed of a single
electronic oscillator that generates a
clock signal, and its
clock domain—the memory elements directly clocked by that signal from that oscillator, and the
combinational logic attached to the outputs of those memory elements.
Because of
speed-of-light delays,
timing skew, etc., the size of a clock domain in such a synchronous system is inversely proportional to the frequency of the clock.
In early computers, typically all the digital logic ran in a single clock domain. Because of
transmission line loss and distortion it is difficult to carry digital signals above 66 MHz on standard
PCB traces (the clock signal is the highest frequency in a synchronous digital system), CPUs that run faster than that speed invariably are
single-chip CPUs with a
phase-locked loop (PLL) or other on-chip oscillator, keeping the fastest signals on-chip. At first, each CPU chip ran in its own single clock domain, and the rest of the digital logic of the computer ran in another slower clock domain. A few modern CPUs have such a high speed clock, that designers are forced to create several different clock domains on a single CPU chip.
Different
clock domains have clocks which have a different
frequency, a different
phase (due to either differing clock latency or a different clock source), or both. Either way the relationship between the clock edges in the two domains cannot be relied upon.
Synchronizing a single bit signal to a clock domain with a higher frequency can be accomplished by registering the signal through a
flip-flop that is clocked by the source domain, thus holding the signal long enough to be detected by the higher frequency clocked destination domain.
To avoid issues with
metastability in the destination domain, a minimum of 2 stages of re-synchronization flip-flops are included in the destination domain.
Synchronizing a single bit signal traversing into clock domain with a slower frequency is more cumbersome. This typically requires a register in each clock domain with a form of feedback from the destination domain to the source domain, indicating that the signal was detected.
In some cases,
clock gating can result in two clock domains where the "slower" domain changes from one second to the next.
See also
*
Crosstalk (electronics)
*
Metastability in electronics
*
Globally asynchronous, locally synchronous
*
Source-synchronous
*
Gray code
*
asynchronous array of simple processors
* The topic is duplicated in
References
Further reading
* (10 pages)
* (17 pages)
* {{cite web |title=1: Clock Domain Crossing |author-first=Peter M. |author-last=Athanas |work=LEDA |series=Course 4514 |publisher=Bradley Department of Electrical and Computer Engineering,
Virginia Tech |location=Blacksburg, Virginia, USA |date=2015 |url=https://filebox.ece.vt.edu/~athanas/4514/ledadoc/html/pol_cdc.html |access-date=2020-08-06 |url-status=live |archive-url=https://web.archive.org/web/20150511034154/https://filebox.ece.vt.edu/~athanas/4514/ledadoc/html/pol_cdc.html |archive-date=2015-05-11
Category:Telecommunication theory
Category:Electronic circuit verification