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The Info List - 31-bit



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In computer architecture , 31-BIT integers , memory addresses , or other data units are those that are 31 bits wide. In 1983, IBM introduced 31-bit addressing in the System/370 -XA mainframe architecture as an upgrade to the 2 4-bit
4-bit
physical and virtual, and transitional 24-bit-virtual/ 26-bit physical, addressing of earlier models. This enhancement allowed address spaces to be 128 times larger, permitting programs to address memory above 16 MiB (referred to as "above the line").

CONTENTS

* 1 Architecture * 2 Transition * 3 370/ESA architecture * 4 z/Architecture * 5 Linux/390 * 6 References

ARCHITECTURE

In the System/360 and early System/370 architectures, the general purpose registers were 32 bits wide, the machine did 32-bit
32-bit
arithmetic operations, and addresses were always stored in 32-bit
32-bit
words, so the architecture was considered 32-bit
32-bit
, but the machines ignored the top 8 bits of the address resulting in 2 4-bit
4-bit
addressing. With the XA extension, no bits in the word were ignored.

TRANSITION

The transition was tricky: assembly language programmers, including IBM's own operating systems architects and developers, had been using the spare byte at the top of addresses for flags for almost twenty years. IBM
IBM
chose to provide two forms of addressing to minimize the pain: if the most significant bit (bit 0) of a 32-bit
32-bit
address was on, the next 31 bits were interpreted as the virtual address. If the most significant bit was off, then only the lower 24 bits were treated as the virtual address (just as with pre-XA systems). Thus programs could continue using the seven low-order bits of the top byte for other purposes as long as they left the top bit off. The only programs requiring modification were those that set the top (leftmost) bit of a word containing an address. This also affected address comparisons: The leftmost bit of a word is also interpreted as a sign-bit in 2's complement arithmetic, indicating a negative number if bit 0 is on. Programs that use signed arithmetic comparison instructions could get reversed results. Two equivalent addresses could be compared as non-equal if one of them had the sign bit turned on even if the remaining bits were identical. Fortunately, most of this was invisible to programmers using high-level languages like COBOL or FORTRAN , and IBM
IBM
aided the transition with dual mode hardware for a period of time.

Certain machine instructions in this 31-bit addressing mode alter the addressing mode bit as a possibly intentional side effect. For example, the original subroutine call instructions BAL, Branch and Link, and its register-register equivalent, BALR, Branch and Link Register, store certain status information, the instruction length code, the condition code and the program mask, in the top byte of the return address. A BAS, Branch and Store, instruction was added to allow 31-bit return addresses. BAS, and its register-register equivalent, BASR, Branch and Store Register, was part of the instruction set of the System/360 Model 67 , which was the only System/360 model to allow addresses longer than 24 bits. These instructions were maintained, but were modified and extended for 31-bit addressing.

Additional instructions in support of 24/ 31-bit addressing include two new register-register call/return instructions which also effect an addressing mode change (e.g. Branch and Save and Set Mode, BASSM, the 24/31 bit version of a call where the linkage address including the mode is saved and a branch is taken to an address in a possibly different mode, and BSM, Branch and Set Mode, the 24/31 bit version of a return, where the return is directly to the previously saved linkage address and in its previous mode). Taken together, BASSM and BSM allow 2 4-bit
4-bit
calls to 31-bit (and return to 24-bit), 31-bit calls to 24-bit (and return to 31-bit), 2 4-bit
4-bit
calls to 2 4-bit
4-bit
(and return to 24-bit) and 31-bit calls to 31-bit (and return to 31-bit).

Like BALR 14,15 (the 24-bit-only form of a call), BASSM is used as BASSM 14,15, where the linkage address and mode are saved in register 14, and a branch is taken to the subroutine address and mode specified in register 15. Somewhat similarly to BCR 15,14 (the 24-bit-only form of an unconditional return), BSM is used as BSM 0,14, where 0 indicates that the current mode is not saved (the program is leaving the subroutine, anyway), and a return to the caller at the address and mode specified in register 14 is to be taken. Refer to IBM
IBM
publication MVS/Extended Architecture System Programming Library: 31-Bit Addressing, GC28-1158-1, for extensive examples of the use of BAS, BASR, BASSM and BSM, in particular, pp. 29–30.

370/ESA ARCHITECTURE

In the 1990s IBM
IBM
introduced 370/ESA architecture (later named 390/ESA and finally ESA/390 or System/390, in short S/390), completing the evolution to full 31-bit virtual addressing and keeping this addressing mode flag. These later architectures allow more than 2 GiB of physical memory and allow multiple concurrent address spaces up to 2 GiB each in size. As of mid-2006 there were too many programs unduly constrained by this multiple 31-bit addressing mode.

Z/ARCHITECTURE

IBM
IBM
broke the 2 GiB linear addressing barrier ("the bar") in 2000 with the introduction of the first 6 4-bit
4-bit
z/Architecture system, the IBM
IBM
zSeries Model 900. Unlike the XA transition, z/Architecture does not reserve a top bit to identify earlier code. z/Architecture maintains compatibility with 2 4-bit
4-bit
and 31-bit code, even older code running concurrently with newer 6 4-bit
4-bit
code.

LINUX/390

Since Linux/390 was first released for the existing 32-bit data/ 31-bit addressing hardware in 1999, initial mainframe Linux applications compiled in pre-z/Architecture mode are also limited to 31-bit addressing. This limitation disappeared with 6 4-bit
4-bit
hardware, 6 4-bit
4-bit
Linux on z Systems , and 6 4-bit
4-bit
Linux applications. The 64-bit Linux distributions still run 32-bit
32-bit
data/ 31-bit addressing programs. IBM's 31-bit addressing allows 31-bit code to make use of additional memory. However, at any one instant, a maximum of 2 GiB is in each working address space. For non-6 4-bit
4-bit
Linux on processors with 31-bit addressing, it is possible to assign memory above the 2 GiB bar as a RAM disk. 31-bit Linux kernel (not user-space) support was removed in version 4.1.

REFERENCES

* ^ Indeed, in a variable length parameter list of addresses, the last address entry traditionally had its most significant bit set to 1, whereas the other address entries were required to have their most significant bit set to 0. * ^ Because the instruction length code is 00b for a BALR and is 01b for a BAL, the high order bit is always guaranteed to be set to 0, thereby indicating 2 4-bit
4-bit
mode, for BALR and BAL on XA and later systems. * ^ "4.1 Merge window, part 1". LWN. April 15, 2015.

* v * t * e

CPU technologies

ARCHITECTURE

* Turing machine
Turing machine
* Post– Turing machine
Turing machine
* Universal Turing machine
Turing machine
* Quantum Turing machine
Turing machine
* Belt machine * Stack machine * Register machine * Counter machine * Pointer machine * Random access machine * Random access stored program machine * Finite-state machine * Queue automaton * Von Neumann * Harvard (Modified ) * Dataflow * TTA * Cellular

* Artificial neural network
Artificial neural network

* Machine learning * Deep learning * Neural processing unit (NPU)

* Convolutional neural network * Load/store architecture * Register memory architecture * Register register architecture * Endianness * FIFO * Zero-copy * NUMA * HUMA * HSA * Heterogeneous computing * Parallel computing * Amorphous computing * Reconfigurable computing * Cognitive computing * DNA computing * Peptide computing * Chemical computing * Organic computing * Wetware computer * Quantum computing * Neuromorphic computing * Optical computing * Reversible computing * Unconventional computing * Hypercomputation * Ternary computer * Symmetric multiprocessing (SMP) * Asymmetric multiprocessing (AMP) * Cache hierarchy * Memory hierarchy

ISA TYPES

* ASIP * CISC * RISC * EDGE (TRIPS ) * VLIW (EPIC ) * MISC * OISC * NISC * ZISC * Comparison

ISAS

* x86 * z/Architecture * ARM * MIPS * Power Architecture ( PowerPC
PowerPC
) * SPARC
SPARC
* VISC * Mill * Itanium ( IA-64 ) * Alpha * Prism * SuperH * Clipper * VAX * Unicore * PA-RISC * MicroBlaze

WORD SIZE

* 1-bit * 2-bit * 4-bit
4-bit
* 8-bit * 9-bit * 10-bit * 12-bit * 15-bit * 16-bit * 1 8-bit * 22-bit * 2 4-bit
4-bit
* 25-bit * 26-bit * 27-bit * 31-bit * 32-bit
32-bit
* 33-bit * 3 4-bit
4-bit
* 36-bit * 39-bit * 40-bit * 4 8-bit * 50-bit * 60-bit * 6 4-bit
4-bit
* 12 8-bit * 256-bit * 5 12-bit * Variable

EXECUTION

* Instruction pipelining

* Bubble * Operand forwarding

* Out-of-order execution

* Register renaming

* Speculative execution

* Branch predictor * Memory dependence prediction

* Hazards

PARALLEL LEVEL

* Bit

* Bit-serial * Word

* Instruction

* Pipelining

* Scalar * Superscalar

* Task

* Thread * Process

* Data

* Vector

* Memory

MULTITHREADING

* Temporal * Simultaneous (SMT) ( Hyper-threading ) * Speculative (SpMT) * Preemptive * Cooperative * Clustered Multi-Thread (CMT) * Hardware scout

FLYNN\\'S TAXONOMY

* SISD * SIMD ( SWAR ) * SIMT * MISD

* MIMD

* SPMD

* Addressing mode

CPU PERFORMANCE

* Instructions per second (IPS) * Instructions per clock (IPC) * Cycles per instruction (CPI) * Floating-point operations per second (FLOPS) * Transactions per second (TPS) * SUPS * Performance per watt * Orders of magnitude (computing) * Cache performance measurement and metric

CORE COUNT

* Single-core processor * Multi-core processor * Manycore processor

TYPES

* Central processing unit (CPU) * GPGPU * AI accelerator * Vision processing unit (VPU) * Vector processor * Barrel processor * Stream processor * Digital signal processor (DSP) * I/O processor/DMA controller * Network processor * Baseband processor * Physics processing unit (PPU) * Coprocessor * Secure cryptoprocessor * ASIC * FPGA
FPGA
* FPOA * CPLD * Microcontroller * Microprocessor * Mobile processor * Notebook processor * Ultra-low-voltage processor * Multi-core processor * Manycore processor * Tile processor * Multi-chip module (MCM) * Chip stack multi-chip modules * System on a chip (SoC) * Network on a chip (NoC) * Multiprocessor system-on-chip (MPSoC) * Programmable System-on-Chip ( PSoC )

COMPONENTS

* Execution unit (EU) * Arithmetic logic unit (ALU) * Address generation unit (AGU) * Floating-point unit (FPU) * Load-store unit (LSU) * Fixed-point unit (FXU) * Vector unit (VU) * Branch predictor * Branch execution unit (BEU) * Instruction Decoder * Instruction Scheduler * Instruction Fetch Unit * Instruction Dispatch Unit * Instruction Sequencing Unit * Unified Reservation Station * Barrel shifter * Uncore * Sum addressed decoder (SAD) * Front-side bus * Back-side bus * Northbridge (computing) * Southbridge (computing) * Adder (electronics) * Binary multiplier * Binary decoder * Address decoder * Multiplexer
Multiplexer
* Demultiplexer
Demultiplexer
* Registers * Cache * Memory management unit
Memory management unit
(MMU) * Input–output memory management unit (IOMMU) * Integrated Memory Controller (IMC) * Power Management Unit (PMU) * Translation lookaside buffer (TLB) * Stack engine * Register file * Processor register * Hardware register * Memory buffer register (MBR) * Program counter * Microcode ROM * Datapath * Control unit * Instruction unit * Re-order buffer * Data buffer * Write buffer * Coprocessor * Electronic switch * Electronic circuit * Integrated circuit
Integrated circuit
* Three-dimensional integrated circuit * Boolean circuit * Digital circuit * Analog circuit * Mixed-signal integrated circuit * Power management integrated circuit * Quantum circuit

* Logic gate

* Combinational logic * Sequential logic * Emitter-coupled logic (ECL) * Transistor–transistor logic
Transistor–transistor logic
(TTL) * Glue logic

* Quantum gate * Gate array * Counter (digital) * Bus (computing)
Bus (computing)
* Semiconductor device * Clock rate * CPU multiplier * Vision chip * Memristor

Power management

* APM * ACPI * Dynamic frequency scaling * Dynamic voltage scaling * Clock gating

Hardware security

* Non-executable memory (NX bit) * Bounds checking (Intel MPX) * Intel Secure Key * Hardware restriction (firmware ) * Software Guard Extensions (Intel SGX) * Trusted Execution Technology * OmniShield * Trusted Platform Module (TPM) * Secure cryptoprocessor * Hardware security module * Hengzhi chip

RELATED

* History of general-purpose CPUs

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