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UltraSPARC
The UltraSPARC is a microprocessor developed by Sun Microsystems and fabricated by Texas Instruments, introduced in mid-1995. It is the first microprocessor from Sun to implement the 64-bit SPARC V9 instruction set architecture (ISA). Marc Tremblay was a co-microarchitect. Microarchitecture The UltraSPARC is a four-issue superscalar microprocessor that executes instructions in in-order. It includes a nine-stage integer pipeline. Functional units The execution units were simplified relative to the SuperSPARC to achieve higher clock frequencies - an example of a simplification is that the ALUs were not cascaded, unlike the SuperSPARC, to avoid restricting clock frequency. The integer register file has 32 64-bit entries. As the SPARC ISA uses register windows, of which the UltraSPARC has eight, the actual number of registers is 144. The register file has seven read and three write ports. The integer register file provides registers to two arithmetic logic unit In c ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
UltraSPARC III
The UltraSPARC III, code-named "Cheetah", is a microprocessor that implements the SPARC V9 instruction set architecture (ISA) developed by Sun Microsystems and fabricated by Texas Instruments. It was introduced in 2001 and operates at 600 to 900 MHz. It was succeeded by the UltraSPARC IV in 2004. Gary Lauterbach was the chief architect. History When presented at the '97 Microprocessor Forum, the probable introduction date for the UltraSPARC III was 1999, and it would have competed with Digital Equipment Corporation's Alpha 21264 and Intel's Itanium (Merced). This was not to be the case as it was delayed until 2001. Despite being late, it was awarded the Analysts' Choice Award for Best Server/Workstation Processor of 2001 by ''Microprocessor Report'' for its multiprocessing features. Description The UltraSPARC III is an in-order superscalar microprocessor. The UltraSPARC III was designed for shared memory multiprocessing performance, and it has several features that ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
UltraSPARC IV
The UltraSPARC IV ''Jaguar'' and follow-up UltraSPARC IV+ ''Panther'' are microprocessors designed by Sun Microsystems and manufactured by Texas Instruments. They are the fourth generation of UltraSPARC microprocessors, and implement the 64-bit SPARC, SPARC V9 instruction set architecture (ISA). The UltraSPARC IV was originally to be succeeded by the UltraSPARC V ''Millennium'', which was canceled after the announcement of the ''Niagara'', now UltraSPARC T1 microprocessor in early 2004. It was instead succeeded by the Fujitsu-designed SPARC64 VI. The UltraSPARC IV was developed as part of Sun's Throughput Computing initiative, which included the UltraSPARC V ''Millennium'', ''Gemini'' and UltraSPARC T1 ''Niagara'' microprocessors. Of the four original designs in the initiative, two reached production: the UltraSPARC IV and the UltraSPARC T1. Whereas the ''Millennium'' and ''Niagara'' implemented Multithreading (computer architecture)#Coarse-grained multithreading, block multithread ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
UltraSPARC II
The UltraSPARC II, code-named "Blackbird", is a microprocessor implementation of the SPARC, SPARC V9 instruction set architecture (ISA) developed by Sun Microsystems. Marc Tremblay was the chief architect. Introduced in 1997, it was further development of the UltraSPARC operating at higher clock rate, clock frequencies of 250 MHz, eventually reaching 650 MHz. The Die (integrated circuit), die contained 5.4 million transistors and had an area of 149 mm. It was Semiconductor device fabrication, fabricated by Texas Instruments in their 0.35 μm process, dissipated 25 W at 205 MHz, and used a 2.5 V power supply. L2 cache capacity was 1 to 4 MB. In 1999, the UltraSPARC II was ported to a 0.25 μm process. This version was code-named "Sapphire-Black". It operated at 360 to 480 MHz, possessed a die area of 126 mm, dissipated 21 W at 400 MHz and the power supply voltage was reduced to 1.9 V. Supported L2 cache capacity was increased to 1 to 8 ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Sun Microsystems
Sun Microsystems, Inc., often known as Sun for short, was an American technology company that existed from 1982 to 2010 which developed and sold computers, computer components, software, and information technology services. Sun contributed significantly to the evolution of several key computing technologies, among them Unix, Reduced instruction set computer, RISC processors, thin client computing, and virtualization, virtualized computing. At its height, the Sun headquarters were in Santa Clara, California (part of Silicon Valley), on the former west campus of the Agnews Developmental Center. Sun products included computer servers and workstations built on its own Reduced instruction set computer, RISC-based SPARC processor architecture, as well as on x86-based AMD Opteron and Intel Xeon processors. Sun also developed its own computer storage, storage systems and a suite of software products, including the Unix-based SunOS and later Solaris operating system, Solaris operating s ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Visual Instruction Set
Visual Instruction Set, or VIS, is a SIMD instruction set extension for SPARC V9 microprocessors developed by Sun Microsystems. There are five versions of VIS: VIS 1, VIS 2, VIS 2+, VIS 3 and VIS 4. History VIS 1 was introduced in 1994 and was first implemented by Sun in their UltraSPARC microprocessor (1995) and by Fujitsu in their SPARC64 GP microprocessors (2000). VIS 2 was first implemented by the UltraSPARC III. All subsequent UltraSPARC and SPARC64 microprocessors implement the instruction set. VIS 3 was first implemented in the SPARC T4 microprocessor. VIS 4 was first implemented in the SPARC M7 microprocessor. Differences vs x86 VIS is not an instruction toolkit like Intel's MMX and SSE. MMX has only 8 registers shared with the FPU stack, while SPARC processors have 32 registers, also aliased to the double-precision (64-bit) floating point registers. As with the SIMD instruction set extensions on other RISC processors, VIS strictly conforms to the main princ ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Marc Tremblay
Marc Tremblay is a distinguished engineer at Microsoft. Prior to joining Microsoft in April 2009, he was senior vice president and chief technology officer of the microelectronics business unit at Sun Microsystems. He was instrumental in the design of various microprocessors at Sun, including the UltraSPARC, UltraSPARC II, MAJC, UltraSPARC T1, and the cancelled Rock processor. In the process, he was awarded more patents than any other Sun employee. Career Tremblay worked at Sun Microsystems for 18 years. In 2009, he joined Microsoft's strategic software/silicon architecture group, led by chief research and strategy officer, Craig Mundie. A team worked under Tremblay developing software semiconductor technologies. The group, known as SiArch, works on green, adaptive and parallel computing. Education He received his bachelor's degree from Laval University in Canada, and both his M.S. (1985) and Ph.D. (1991) degrees from UCLA. References External links All Marc Tre ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Out-of-order Execution
In computer engineering, out-of-order execution (or more formally dynamic execution) is an instruction scheduling paradigm used in high-performance central processing units to make use of instruction cycles that would otherwise be wasted. In this paradigm, a processor executes instructions in an order governed by the availability of input data and execution units, rather than by their original order in a program. In doing so, the processor can avoid being idle while waiting for the preceding instruction to complete and can, in the meantime, process the next instructions that are able to run immediately and independently. History Out-of-order execution is a restricted form of dataflow architecture, which was a major research area in computer architecture in the 1970s and early 1980s. Early use in supercomputers The first machine to use out-of-order execution was the CDC 6600 (1964), designed by James E. Thornton, which uses a scoreboard to avoid conflicts. It permits ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
64-bit Microprocessors
In computer architecture, 64-bit integers, memory addresses, or other data units are those that are 64 bits wide. Also, 64-bit central processing units (CPU) and arithmetic logic units (ALU) are those that are based on processor registers, address buses, or data buses of that size. A computer that uses such a processor is a 64-bit computer. From the software perspective, 64-bit computing means the use of machine code with 64-bit virtual memory addresses. However, not all 64-bit instruction sets support full 64-bit virtual memory addresses; x86-64 and AArch64, for example, support only 48 bits of virtual address, with the remaining 16 bits of the virtual address required to be all zeros (000...) or all ones (111...), and several 64-bit instruction sets support fewer than 64 bits of physical memory address. The term ''64-bit'' also describes a generation of computers in which 64-bit processors are the norm. 64 bits is a word size that defines certain classes of computer archit ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SuperSPARC
The SuperSPARC is a microprocessor that implements the SPARC V8 instruction set architecture (ISA) developed by Sun Microsystems. 33 and 40 MHz versions were introduced in 1992. The SuperSPARC contains 3.1 million transistors. It was fabricated by Texas Instruments (TI) at Miho, Japan in a 0.8 micrometre triple-metal BiCMOS process. There are two derivatives of the SuperSPARC: the SuperSPARC+ and SuperSPARC-II. The SuperSPARC+ was developed to remedy some of the design flaws that limited the SuperSPARC's clock frequency and thus performance. The SuperSPARC-II, introduced in 1994, was a major revision with improvements that enabled the microprocessor to reach 85 MHz in desktop systems and 90 MHz in the more heavily cooled SPARCserver-1000E. SuperSPARC CPU modules are used in both the SPARCstation 10 and SPARCstation 20. The SuperSPARC-II was replaced in 1995 by the 64-bit UltraSPARC, an implementation of the 64-bit In computer architecture, 64-bit integer ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Microprocessor
A microprocessor is a computer processor (computing), processor for which the data processing logic and control is included on a single integrated circuit (IC), or a small number of ICs. The microprocessor contains the arithmetic, logic, and control circuitry required to perform the functions of a computer's central processing unit (CPU). The IC is capable of interpreting and executing program instructions and performing arithmetic operations. The microprocessor is a multipurpose, Clock signal, clock-driven, Processor register, register-based, digital integrated circuit that accepts binary code, binary data as input, processes it according to instruction (computing), instructions stored in its computer memory, memory, and provides results (also in binary form) as output. Microprocessors contain both combinational logic and sequential logic, sequential digital logic, and operate on numbers and symbols represented in the binary number system. The integration of a whole CPU on ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Superscalar
A superscalar processor (or multiple-issue processor) is a CPU that implements a form of parallelism called instruction-level parallelism within a single processor. In contrast to a scalar processor, which can execute at most one single instruction per clock cycle, a superscalar processor can execute or start executing more than one instruction during a clock cycle by simultaneously dispatching multiple instructions to different execution units on the processor. It therefore allows more throughput (the number of instructions that can be executed in a unit of time which can even be less than 1) than would otherwise be possible at a given clock rate. Each execution unit is not a separate processor (or a core if the processor is a multi-core processor), but an execution resource within a single CPU such as an arithmetic logic unit. While a superscalar CPU is typically also pipelined, superscalar and pipelining execution are considered different performance enhancement techni ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Ball Grid Array
A ball grid array (BGA) is a type of surface-mount packaging (a chip carrier) used for integrated circuits. BGA packages are used to permanently mount devices such as microprocessors. A BGA can provide more interconnection pins than can be put on a dual in-line or flat package. The whole bottom surface of the device can be used, instead of just the perimeter. The traces connecting the package's leads to the wires or balls which connect the die to package are also on average shorter than with a perimeter-only type, leading to better performance at high speeds. Soldering of BGA devices requires precise control and is usually done by automated processes such as in computer-controlled automatic reflow ovens. Description The BGA is descended from the pin grid array (PGA), which is a package with one face covered (or partly covered) with pins in a grid pattern which, in operation, conduct electrical signals between the integrated circuit and the printed circuit board (PCB) ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
