A model-specific register (MSR) is any of various

control register A control register is a processor register which changes or controls the general behavior of a CPU or other digital device. Common tasks performed by control registers include interrupt control, switching the addressing mode, paging control, ...

s in the

x86 x86 (also known as 80x86 or the 8086 family) is a family of complex instruction set computer (CISC) instruction set architectures initially developed by Intel based on the Intel 8086 microprocessor and its 8088 variant. The 8086 was introd ...

instruction set In computer science, an instruction set architecture (ISA), also called computer architecture, is an abstract model of a computer. A device that executes instructions described by that ISA, such as a central processing unit (CPU), is called an ' ...

used for

debugging In computer programming and software development, debugging is the process of finding and resolving '' bugs'' (defects or problems that prevent correct operation) within computer programs, software, or systems. Debugging tactics can involve in ...

, program execution tracing,

computer performance In computing, computer performance is the amount of useful work accomplished by a computer system. Outside of specific contexts, computer performance is estimated in terms of accuracy, efficiency and speed of executing computer program instructio ...

monitoring, and toggling certain CPU features.

History

With the introduction of the 80386 processor, Intel began introducing "experimental" features that would not necessarily be present in future versions of the processor. The first of these were two "test registers" (TR6 and TR7) that enabled testing of the processor's

translation lookaside buffer A translation lookaside buffer (TLB) is a memory cache that stores the recent translations of virtual memory to physical memory. It is used to reduce the time taken to access a user memory location. It can be called an address-translation cache. ...

(TLB); a special variant of the instruction allowed moving to and from the test registers. Three additional test registers followed in the 80486 (TR3–TR5) that enabled testing of the processor's caches for code and data. None of these five registers were implemented in the subsequent Pentium processor; the special variant of generated an invalid opcode exception. With the introduction of the Pentium processor, Intel provided a pair of instructions ( and ) to access current and future "model-specific registers", as well as the instruction to determine which features are present on a particular model. Many of these registers have proven useful enough to be retained. Intel has classified these as ''architectural'' model-specific registers and has committed to their inclusion in future product lines.

Using MSRs

Reading and writing to these registers is handled by the rdmsr and wrmsr instructions, respectively. As these are privileged instructions, they can be executed only by the operating system. Use of the Linux ''msr'' kernel module creates a pseudo file "/dev/cpu/''x''/msr" (with a unique ''x'' for each processor or processor core). A user with permissions to read and/or write to this file can use the file I/O API to access these registers. The ''msr-tools''msr-tools
at 01.org package provides a reference implementation. Documentation regarding which MSRs a certain processor implementation supports is usually found in the processor documentation of the CPU vendor. Examples for rather well-known MSRs are the

memory type range register Memory type range registers (MTRRs) are a set of processor supplementary capability control registers that provide system software with control of how accesses to memory ranges by the CPU are cached. It uses a set of programmable model-specifi ...

s (MTRRs) and the

address-range register Address-range registers (ARR) are control registers of the Cyrix 6x86, 6x86MX and MII processors that are used as a control mechanism which provides system software with control of how accesses to memory ranges by the CPU are cached, similar to w ...

s (ARRs).

References

{{Reflist

External links

*https://www.coreboot.org/Msrtool Digital registers Instruction processing X86 architecture X86 instructions

History

Using MSRs

See also

References

External links