computer architecture In computer engineering, computer architecture is a description of the structure of a computer system made from component parts. It can sometimes be a high-level description that ignores details of the implementation. At a more detailed level, the ...

and

engineering Engineering is the use of scientific principles to design and build machines, structures, and other items, including bridges, tunnels, roads, vehicles, and buildings. The discipline of engineering encompasses a broad range of more speciali ...

, a sequencer or microsequencer generates the addresses used to step through the microprogram of a

control store A control store is the part of a CPU's control unit that stores the CPU's microprogram. It is usually accessed by a microsequencer. A control store implementation whose contents are unalterable is known as a Read Only Memory (ROM) or Read Only S ...

. It is used as a part of the

control unit The control unit (CU) is a component of a computer's central processing unit (CPU) that directs the operation of the processor. A CU typically uses a binary decoder to convert coded instructions into timing and control signals that direct the op ...

of a CPU or as a stand-alone generator for address ranges. Usually the addresses are generated by some combination of a counter, a field from a microinstruction, and some subset of the instruction register. A counter is used for the typical case, that the next microinstruction is the one to execute. A field from the microinstruction is used for jumps, or other logic. Since CPUs implement an instruction set, it's very useful to be able to decode the instruction's

bit The bit is the most basic unit of information in computing and digital communications. The name is a portmanteau of binary digit. The bit represents a logical state with one of two possible values. These values are most commonly represente ...

s directly into the sequencer, to select a set of microinstructions to perform a CPU's instructions. Most modern CISC processors use a combination of pipelined logic to process lower complexity opcodes which can be completed in one clock cycle, and microcode to implement ones that take multiple clock cycles to complete. One of the first integrated microcoded processors was the

IBM PALM Processor The PALM (Put All Logic in Microcode) is a 16-bit central processing unit (CPU) developed by IBM. It was used in the IBM 5100 Portable Computer, a predecessor of the IBM PC, and the IBM 5110 and IBM 5120 follow-on machines. It is likely PALM wa ...

, which emulated all of the processor's instruction in microcode and was used on the

IBM 5100 The IBM 5100 Portable Computer is a portable computer (one of the first) introduced in September 1975, six years before the IBM Personal Computer, and eight before the first successful IBM compatible portable computer, the Compaq Portable. It ...

, one of the first personal computers. Recent examples of similar open-sourced microsequencer-based processors are the MicroCore Lab
MCL86

MCL51
, an
MCL65
cores which emulate the Intel 8086/8088, 8051 and MOS 6502 instruction sets entirely in microcode.

Simple example

Th
Digital Scientific Corp.
Meta 4 Series 16 computer system was a user-microprogrammable system first available in 1970. Branches in the microcode sequence occur in one of three ways. * A

branch A branch, sometimes called a ramus in botany, is a woody structural member connected to the central trunk of a tree (or sometimes a shrub). Large branches are known as boughs and small branches are known as twigs. The term ''twig'' usually ...

microinstruction specifies the address of the next instruction, either conditionally or unconditionally. The logical index (IX) option causes the 16-bit Link register to be logical ORed into the branch address, thus providing a simple indexed branch capability. * All the arithmetic/logical instructions allow the jump (J) modifier, which redirects execution to the microinstruction addressed by the Link register. * All the arithmetic/logical instructions allow both the decrement counter (D) and jump (J) modifiers. In this case, the 8-bit loop counter register is decremented. If it is then not zero, a branch is taken to the contents of the Link register. If it is zero, execution continues with the next instruction. One more sequencing option allowed on a branch instruction is the execute (XQ) option. When specified, the single instruction at the branch address is executed, but then execution continues after the original branch instruction. The IX option can be used with the XQ option.

Complex example

The IBM System/360 was a series of compatible computers introduced in 1964, many of which were microprogrammed. The System/360 Model 40 is a good example of a microprogrammed machine with complex microsequencing. The microstore consists of 4,096 56-bit microinstructions that operate in a horizontal microprogramming style. The store is addressed by the 12-bit read-only address register (ROAR). Unlike most registers in the S/360 architecture, bits in the ROAR are numbered from bit 0 on the right to bit 11 on the left.

  +------------+
  ,     ROAR    , 
  +------------+
  11          0

The model 40 performs no sequential execution of microinstructions and therefore the microsequencer doesn't really branch in the conventional sense. Instead, each microinstruction specifies the address of the next one to be executed. Four fields in the microinstruction contribute to the new address. * CA, 4 bits: Part of the next address, depending on the other fields. * CB, 4 bits: Determines bit 1 of the next address. * CC, 4 bits: Determines bit 0 of the next address. * CD, 2 bits: Controls how the next address is assembled (except when the CB field contains 15). There are essentially three combinations or formats of these fields.

Functional branch format

When the CB field contains 15, a ''functional branch'' occurs. The bits of the new microstore address in the ROAR are determined as follows. * bits 11–10: CD field * bits 9–6: CA field * bit 5: always 0 * bits 4–1: high-order 4 bits of the Q register, which is the right input to the 8-bit ALU * bit 0: result of the test specified by the CC field The CC field can specify various tests of the state of the machine. It can also specify a constant 0 or 1 for an unconditional bit. This format alters the flow of control to 1 of 16 instruction ''pairs'' within the low 32 words of a 64-word block of microstore (because bit 5 is always 0). The CC field then determines which instruction of the pair receives control.

CD = 0, 1, 3 format

When the CD field is 0, 1, or 3, flow of control is directed to an instruction within the current 64-word block. The bits of the new microstore address are determined as follows. * bits 11–6: remain the same * bits 5–2: CA field * bit 1: if CD = 0, result of the test specified by the CB field; otherwise 0 * bit 0: result of the test specified by the CC field The CA field selects 1 of 16 4-word groups within the current 64-word block. The CB and CC fields then determine which instruction of the 4 receives control.

CD = 2 format

When the CD field is 2, flow of control is directed in a nonobvious manner. The bits of the new microstore address are determined as follows: * bits 11–10: remain the same * bits 9–6: CA field * bits 5–2: remain the same * bit 1: result of the test specified by the CB field * bit 0: result of the test specified by the CC field The next instruction is in the same 1K-word region as the current instruction, because bits 11–10 remain the same. The CA field determines the 64-word block within the region. The instruction is in the same 4-word group within the new block as the current instruction is within the current block, because bits 5–2 remain the same. The CB and CC fields then determine which instruction of the 4 receives control.

Simplification

This description has been simplified. It ignores the following features. * The model 40 can run in CPU mode or channel mode. The description addresses only CPU mode. * If the microinstruction is not in functional branch format and the CD field is 1 or 3, bit 1 of the next address is always 0. In this case, the values of the CD and CB fields determine one of a set of control lines to raise.

References

{{CPU technologies Central processing unit