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A lookahead carry unit (LCU) is a logical unit in
digital circuit In theoretical computer science, a circuit is a model of computation in which input values proceed through a sequence of gates, each of which computes a function. Circuits of this kind provide a generalization of Boolean circuits and a mathemati ...
design used to decrease calculation time in adder units and used in conjunction with
carry look-ahead adder A carry-lookahead adder (CLA) or fast adder is a type of electronics adder used in digital logic. A carry-lookahead adder improves speed by reducing the amount of time required to determine carry bits. It can be contrasted with the simpler, b ...
s (CLAs).


4-bit adder

A single 4-bit CLA is shown below:


16-bit adder

By combining four 4-bit CLAs, a 16-bit adder can be created but additional logic is needed in the form of an LCU. The LCU accepts the group propagate (P_G) and group generate (G_G) from each of the four CLAs. P_G and G_G have the following expressions for each CLA adder: :P_G = P_3 \cdot P_2 \cdot P_1 \cdot P_0 :G_G = G_3 + P_3 \cdot G_2 + P_3 \cdot P_2 \cdot G_1 + P_3 \cdot P_2 \cdot P_1 \cdot G_0 The LCU then generates the carry input for each CLA. Assume that P_i is P_G and G_i is G_G from the ith CLA then the output carry bits are :C_ = G_0 + P_0 \cdot C_0 :C_ = G_ + P_ \cdot C_ :C_ = G_ + P_ \cdot C_ :C_ = G_ + P_ \cdot C_ Substituting C_ into C_, then C_ into C_, then C_ into C_ yields the expanded equations: :C_ = G_0 + P_0 \cdot C_0 :C_ = G_4 + G_0 \cdot P_4 + C_0 \cdot P_0 \cdot P_4 :C_ = G_8 + G_4 \cdot P_8 + G_0 \cdot P_4 \cdot P_8 + C_0 \cdot P_0 \cdot P_4 \cdot P_8 :C_ = G_ + G_8 \cdot P_ + G_4 \cdot P_8 \cdot P_ + G_0 \cdot P_4 \cdot P_8 \cdot P_ + C_0 \cdot P_0 \cdot P_4 \cdot P_8 \cdot P_ C_ corresponds to the carry input into the second CLA; C_ to the third CLA; C_ to the fourth CLA; and C_ to overflow carry bit. In addition, the LCU can calculate its own propagate and generate: :P_ = P_0 \cdot P_4 \cdot P_8 \cdot P_ :G_ = G_ + G_8 \cdot P_ + G_4 \cdot P_8 \cdot P_ + G_0 \cdot P_4 \cdot P_8 \cdot P_ :C_ = G_ + C_0 \cdot P_


64-bit adder

By combining 4 CLAs and an LCU together creates a 16-bit adder. Four of these units can be combined to form a 64-bit adder. An additional (second-level) LCU is needed that accepts the propagate (P_) and generate (G_) from each LCU and the four carry outputs generated by the second-level LCU are fed into the first-level LCUs.


References

* * {{cite book , last=Vahid , first=Frank , title=Digital Design , url=https://archive.org/details/digitaldesign00vahi , url-access=limited , publisher=John Wiley and Sons Publishers , year=2006 , isbn=0-470-04437-3 , page
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