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A status register, flag register, or condition code register (CCR) is a collection of status
flag A flag is a piece of fabric (most often rectangular or quadrilateral) with a distinctive design and colours. It is used as a symbol, a signalling device, or for decoration. The term ''flag'' is also used to refer to the graphic design empl ...
bit The bit is the most basic unit of information in computing and digital communications. The name is a portmanteau of binary digit. The bit represents a logical state with one of two possible values. These values are most commonly represente ...
s for a
processor Processor may refer to: Computing Hardware * Processor (computing) **Central processing unit (CPU), the hardware within a computer that executes a program *** Microprocessor, a central processing unit contained on a single integrated circuit (I ...
. Examples of such registers include
FLAGS register The FLAGS register is the status register that contains the current state of a x86 CPU. The size and meanings of the flag bits are architecture dependent. It usually reflects the result of arithmetic operations as well as information about restrict ...
in the
x86 architecture x86 (also known as 80x86 or the 8086 family) is a family of complex instruction set computer (CISC) instruction set architectures initially developed by Intel based on the Intel 8086 microprocessor and its 8088 variant. The 8086 was int ...
, flags in the
program status word The program status word (PSW) is a register that performs the function of a status register and program counter, and sometimes more. The term is also applied to a copy of the PSW in storage. This article only discusses the PSW in the IBM System/3 ...
(PSW) register in the IBM System/360 architecture through
z/Architecture z/Architecture, initially and briefly called ESA Modal Extensions (ESAME), is IBM's 64-bit complex instruction set computer (CISC) instruction set architecture, implemented by its mainframe computers. IBM introduced its first z/Architect ...
, and the application program status register (APSR) in the
ARM Cortex-A The ARM Cortex-A is a group of 32-bit and 64-bit RISC ARM processor cores licensed by Arm Holdings. The cores are intended for application use. The group consists of 32-bit only cores: ARM Cortex-A5, ARM Cortex-A7, ARM Cortex-A8, ARM Cortex-A9, ...
architecture. The status register is a
hardware register In digital electronics, especially computing, hardware registers are circuits typically composed of flip flops, often with many characteristics similar to memory, such as: * The ability to read or write multiple bits at a time, and * Using an ...
that contains information about the state of the
processor Processor may refer to: Computing Hardware * Processor (computing) **Central processing unit (CPU), the hardware within a computer that executes a program *** Microprocessor, a central processing unit contained on a single integrated circuit (I ...
. Individual bits are implicitly or explicitly read and/or written by the
machine code In computer programming, machine code is any low-level programming language, consisting of machine language instructions, which are used to control a computer's central processing unit (CPU). Each instruction causes the CPU to perform a ve ...
instructions executing on the processor. The status register lets an instruction take action contingent on the outcome of a previous instruction. Typically, flags in the status register are modified as effects of arithmetic and bit manipulation operations. For example, a Z bit may be set if the result of the operation is zero and cleared if it is nonzero. Other classes of instructions may also modify the flags to indicate status. For example, a string instruction may do so to indicate whether the instruction terminated because it found a match/mismatch or because it found the end of the string. The flags are read by a subsequent conditional instruction so that the specified action (depending on the processor, a jump, call, return, or so on) occurs only if the flags indicate a specified result of the earlier instruction. Some CPU architectures, such as the MIPS and
Alpha Alpha (uppercase , lowercase ; grc, ἄλφα, ''álpha'', or ell, άλφα, álfa) is the first letter of the Greek alphabet. In the system of Greek numerals, it has a value of one. Alpha is derived from the Phoenician letter aleph , whi ...
, do not use a dedicated flag register. Others do not implicitly set and/or read flags. Such machines either do not pass ''implicit'' status information between instructions at all, or they pass it in an explicitly selected general purpose register. A status register may often have other fields as well, such as more specialized flags,
interrupt In digital computers, an interrupt (sometimes referred to as a trap) is a request for the processor to ''interrupt'' currently executing code (when permitted), so that the event can be processed in a timely manner. If the request is accepted, ...
enable bits, and similar types of information. During an interrupt, the status of the thread currently executing can be preserved (and later recalled) by storing the current value of the status register along with the
program counter The program counter (PC), commonly called the instruction pointer (IP) in Intel x86 and Itanium microprocessors, and sometimes called the instruction address register (IAR), the instruction counter, or just part of the instruction sequencer, i ...
and other active registers into the machine stack or some other reserved area of memory.


Common flags

This is a list of the most common CPU status register flags, implemented in almost all modern processors.


Other flags

On some processors, the status register also contains flags such as these:


CPU architectures without arithmetic flags

Status flags enable an instruction to act based on the result of a previous instruction. In pipelined processors, such as
superscalar A superscalar processor is a CPU that implements a form of parallelism called instruction-level parallelism within a single processor. In contrast to a scalar processor, which can execute at most one single instruction per clock cycle, a sup ...
and
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processors, this can create
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that slow processing or require extra hardware to work around them. Some
very long instruction word Very long instruction word (VLIW) refers to instruction set architectures designed to exploit instruction level parallelism (ILP). Whereas conventional central processing units (CPU, processor) mostly allow programs to specify instructions to exe ...
processors dispense with the status flags. A single instruction both performs a test and indicates on which outcome of that test to take an action, such as Compare ''a'' with ''b'' and Jump to ''c'' if Equal. The result of the test is not saved for subsequent instructions. Another alternative to the status register is for processor instructions to deposit status information in a general-purpose register when the program requests it. MIPS,
AMD 29000 The AMD Am29000, commonly shortened to 29k, is a family of 32-bit RISC microprocessors and microcontrollers developed and fabricated by Advanced Micro Devices (AMD). Based on the seminal Berkeley RISC, the 29k added a number of significant impr ...
,
DEC Alpha Alpha (original name Alpha AXP) is a 64-bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by Digital Equipment Corporation (DEC). Alpha was designed to replace 32-bit VAX complex instruction set compute ...
, and
RISC-V RISC-V (pronounced "risk-five" where five refers to the number of generations of RISC architecture that were developed at the University of California, Berkeley since 1981) is an open standard instruction set architecture (ISA) based on est ...
are examples of architectures that provide comparison instructions that store the comparison result in a general-purpose register, as a single bit or a numeric value of 0 or 1. Conditional branches act based on the value in the general-purpose register. Usually, comparison instructions test equality or signed/unsigned magnitude. To test for other conditions, a program uses an equivalence formula. For example, MIPS has no "carry bit" but a program performing multiple-word addition can test whether a single-word addition of registers overflowed by testing whether the sum is lower than an operand: # alow = blow + clow addu alow, blow, clow # set tmp = 1 if alow < clow, else 0 sltu tmp, alow, clow addu ahigh, bhigh, chigh addu ahigh, ahigh, tmp The sltu instruction sets tmp to 1 or 0 based on the specified comparison of its two other operands. (Here, the general-purpose register tmp is not used as a status register to govern a conditional jump; rather, the possible value of 1, indicating carry from the low-order addition, is added to the high-order word.) This scheme becomes less convenient when adding three or more words, as there are two additions when computing b + c + tmp, either of which may generate a carry, which must be detected with two sltu instructions. Fortunately, those two carries may be added to each other without risk of overflow, so the situation stabilizes at five instructions per word added.


See also

*
Control register A control register is a processor register which changes or controls the general behavior of a CPU or other digital device. Common tasks performed by control registers include interrupt control, switching the addressing mode, paging control, ...
*
CPU flag (x86) In the x86 architecture, the CPUID instruction (identified by a CPUID opcode) is a processor supplementary instruction (its name derived from CPU IDentification) allowing software to discover details of the processor. It was introduced by Intel i ...
*
Flag field A bit field is a data structure that consists of one or more adjacent bits which have been allocated for specific purposes, so that any single bit or group of bits within the structure can be set or inspected. A bit field is most commonly used to r ...


References

{{DEFAULTSORT:Status Register Control flow Central processing unit Digital registers