A control register is a
processor register which changes or controls the general behavior of a
CPU
A central processing unit (CPU), also called a central processor, main processor or just processor, is the electronic circuitry that executes instructions comprising a computer program. The CPU performs basic arithmetic, logic, controlling, a ...
or other digital device. Common tasks performed by control registers include
interrupt control, switching the
addressing mode,
paging control, and
coprocessor control.
Control registers in x86 series
CR0
The CR0 register is 32 bits long on the
386 and higher processors. On
x64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging mod ...
processors in
long mode, it (and the other control registers) is 64 bits long. CR0 has various control flags that modify the basic operation of the processor. Register CR0 is the 32 Bit version of the old
Machine Status Word (MSW) register. The MSW register was expanded to the Control Register with the appearance of the i386 processor.
CR1
Reserved, the CPU will throw a #
UD exception when trying to access it.
CR2
Contains a value called Page Fault Linear Address (PFLA). When a page fault occurs, the address the program attempted to access is stored in the CR2 register.
CR3
Used when
virtual addressing is enabled, hence when the PG bit is set in CR0. CR3 enables the processor to translate linear addresses into physical addresses by locating the page directory and
page table
A page table is the data structure used by a virtual memory system in a computer operating system to store the mapping between virtual addresses and physical addresses. Virtual addresses are used by the program executed by the accessing Process ( ...
s for the current task. Typically, the upper 20 bits of CR3 become the ''page directory base register'' (PDBR), which stores the physical address of the first page directory. If the PCIDE bit in
CR4 is set, the lowest 12 bits are used for the
process-context identifier (PCID).
CR4
Used in protected mode to control operations such as virtual-8086 support, enabling I/O breakpoints,
page size extension and
machine-check exceptions.
CR5-7
Reserved, same case as CR1.
Additional Control registers in x86-64 series
EFER
Extended Feature Enable Register (EFER) is a
model-specific register added in the
AMD K6 processor, to allow enabling the
SYSCALL/SYSRET instruction, and later for entering and exiting
long mode. This register becomes architectural in
AMD64 and has been adopted by
Intel
Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California. It is the world's largest semiconductor chip manufacturer by revenue, and is one of the developers of the x86 ser ...
as IA32_EFER. Its MSR number is 0xC0000080.
CR8
CR8 is a new register accessible in 64-bit mode using the REX prefix. CR8 is used to prioritize external
interrupts
In digital computers, an interrupt (sometimes referred to as a trap) is a request for the processor to ''interrupt'' currently executing code (when permitted), so that the event can be processed in a timely manner. If the request is accepted, ...
and is referred to as the task-priority register (TPR).
The
AMD64 architecture allows software to define up to 15 external interrupt-priority classes. Priority classes are numbered from 1 to 15, with priority-class 1 being the lowest and priority-class 15 the highest. CR8 uses the four low-order bits for specifying a
task priority and the remaining 60 bits are reserved and must be written with zeros.
System software can use the TPR register to temporarily block low-priority interrupts from interrupting a high-priority task. This is accomplished by loading TPR with a value corresponding to the highest-priority interrupt that is to be blocked. For example, loading TPR with a value of 9 (1001b) blocks all interrupts with a priority class of 9 or less, while allowing all interrupts with a priority class of 10 or more to be recognized. Loading TPR with 0 enables all external interrupts. Loading TPR with 15 (1111b) disables all external interrupts.
The TPR is cleared to 0 on reset.
XCR0 and XSS
XCR0, or Extended Control Register 0, is a control register which is used to toggle the storing or loading of registers related to specific CPU features using the XSAVE/XRSTOR instructions. It is also used with some features to enable or disable the processor's ability to execute their corresponding instructions. It can be accessed using the privileged XSETBV and nonprivileged XGETBV instructions.
There is also the IA32_XSS MSR, which is located at address 0DA0h. The IA32_XSS MSR controls bits of XCR0 which are considered to be "supervisor" state, and should be invisible to regular programs. It operates with the privileged XSAVES and XRSTORS instructions by adding supervisor state to the data they operate with. Put simply, if the X87 state was enabled in XCR0 and PT state was enabled in IA32_XSS, the XSAVE instruction would only store X87 state, while the privileged XSAVES would store both X87 and PT states. Because it is an MSR, it can be accessed using the RDMSR and WRMSR instructions.
See also
*
General-purpose register
*
Test register A test register, in the Intel 80386 and Intel 80486 processor, was a register used by the processor, usually to do a self-test. Most of these registers were undocumented, and used by specialized software. The test registers were named TR3 to TR7. R ...
*
Model-specific register
*
Debug register
*
Flag byte
*
Status register
References
External links
{{wikibooks, X86 Assembly/Protected Mode
Intel 64 and IA-32 Architectures Developer's Manual: Vol. 3AIntel 64 and IA-32 Architectures Software Developer ManualsTech Docs: AMD64Wyatt's World: Cracking Open the Pentium III(1999-05-28)
Operating system technology
Central processing unit
Digital registers