Zero Register
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A zero register is a
processor register A processor register is a quickly accessible location available to a computer's processor. Registers usually consist of a small amount of fast storage, although some registers have specific hardware functions, and may be read-only or write-only. ...
that always returns the value zero. It is found primarily in high-performance
instruction set architecture In computer science, an instruction set architecture (ISA), also called computer architecture, is an abstract model of a computer. A device that executes instructions described by that ISA, such as a central processing unit (CPU), is called an ' ...
s, notably the CDC 6600,
System/360 The IBM System/360 (S/360) is a family of mainframe computer systems that was announced by IBM on April 7, 1964, and delivered between 1965 and 1978. It was the first family of computers designed to cover both commercial and scientific applica ...
and MIPS architecture, among others. Zero appears as a constant in many instructions, notably "branch if zero", and optimizing these instructions can have a significant positive benefit on performance. Some architectures accomplish this with dedicated
opcode In computing, an opcode (abbreviated from operation code, also known as instruction machine code, instruction code, instruction syllable, instruction parcel or opstring) is the portion of a machine language instruction that specifies the operat ...
s, specialized variations of their basic instructions. Implementing these requires additional logic in the
instruction decoder A central processing unit (CPU), also called a central processor, main processor or just processor, is the electronic circuitry that executes instructions comprising a computer program. The CPU performs basic arithmetic, logic, controlling, an ...
. The zero register can accomplish the same effect without requiring new opcodes, although at the cost of dedicating a register to this feature, which can be expensive in circuitry terms.


References

* {{comp-stub Computer architecture