Value Change Dump (VCD) (also known less commonly as "Variable Change Dump") is an

ASCII ASCII ( ), abbreviated from American Standard Code for Information Interchange, is a character encoding standard for electronic communication. ASCII codes represent text in computers, telecommunications equipment, and other devices. Because ...

-based format for dumpfiles generated by

EDA EDA or Eda may refer to: Computing * Electronic design automation * Enterprise Desktop Alliance, a computer technology consortium * Enterprise digital assistant * Estimation of distribution algorithm * Event-driven architecture * Exploratory ...

logic simulation Logic simulation is the use of simulation software to predict the behavior of digital circuits and hardware description languages. Simulation can be performed at varying degrees of physical abstraction, such as at the transistor level, gate le ...

tools. The standard, four-value VCD format was defined along with the

Verilog Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction. It is als ...

hardware description language In computer engineering, a hardware description language (HDL) is a specialized computer language used to describe the structure and behavior of electronic circuits, and most commonly, digital logic circuits. A hardware description language en ...

by the

IEEE The Institute of Electrical and Electronics Engineers (IEEE) is a 501(c)(3) professional association for electronic engineering and electrical engineering (and associated disciplines) with its corporate office in New York City and its operat ...

Standard 1364-1995 in 1996. An Extended VCD format defined six years later in the IEEE Standard 1364-2001 supports the logging of signal strength and directionality. The simple and yet compact structure of the VCD format has allowed its use to become ubiquitous and to spread into non-Verilog tools such as the

VHDL The VHSIC Hardware Description Language (VHDL) is a hardware description language (HDL) that can model the behavior and structure of digital systems at multiple levels of abstraction, ranging from the system level down to that of logic gate ...

simulator GHDL and various

kernel Kernel may refer to: Computing * Kernel (operating system), the central component of most operating systems * Kernel (image processing), a matrix used for image convolution * Compute kernel, in GPGPU programming * Kernel method, in machine learn ...

tracers. A limitation of the format is that it is unable to record the values in memories.

Structure/syntax

The VCD file comprises a header section with date, simulator, and timescale information; a variable definition section; and a value change section, in that order. The sections are not explicitly delineated within the file, but are identified by the inclusion of keywords belonging to each respective section. VCD keywords are marked by a leading $ (but variable identifiers can also start with a $). In general every keyword starts a section which is terminated by an $end keyword. All VCD tokens are delineated by whitespace. Data in the VCD file is case sensitive.

Header section

The header section of the VCD file includes a

timestamp A timestamp is a sequence of characters or encoded information identifying when a certain event occurred, usually giving date and time of day, sometimes accurate to a small fraction of a second. Timestamps do not have to be based on some absolut ...

, a

simulator A simulation is the imitation of the operation of a real-world process or system over time. Simulations require the use of models; the model represents the key characteristics or behaviors of the selected system or process, whereas the s ...

version number, and a timescale, which maps the time increments listed in the value change section to simulation time units.

Variable definition section

The variable definition section of the VCD file contains scope information as well as lists of signals instantiated in a given scope. Each variable is assigned an arbitrary, compact ASCII identifier for use in the value change section. The identifier is composed of printable ASCII characters from ! to ~ (decimal 33 to 126). Several variables can share an identifier if the simulator determines that they will always have the same value. The scope type definitions closely follow Verilog concepts, and include the types ''module'', ''task'', ''function'', and ''fork''.

$dumpvars section

The section beginning with $dumpvars keyword contains initial values of all variables dumped.

Value change section

The value change section contains a series of time-ordered value changes for the signals in a given simulation model. The current time is indicated by '#' followed by the timestamp. For scalar (single bit) signal the format is signal value denoted by 0 or 1 followed immediately by the signal identifier with no space between the value and the signal identifier. For vector (multi-bit) signals the format is signal value denoted by letter 'b' or 'B' followed by the value in binary format followed by space and then the signal identifier. Value for real variables is denoted by letter 'r' or 'R' followed by the data using %.16g printf() format followed by space and then the variable identifier.

Example VCD file

$date Date text. For example: November 11, 2009. $end $version VCD generator tool version info text. $end $comment Any comment text. $end $timescale 1ps $end $scope module logic $end $var wire 8 # data $end $var wire 1 $ data_valid $end $var wire 1 % en $end $var wire 1 & rx_en $end $var wire 1 ' tx_en $end $var wire 1 ( empty $end $var wire 1 ) underrun $end $upscope $end $enddefinitions $end $dumpvars bxxxxxxxx # x$ 0% x& x' 1( 0) $end #0 b10000001 # 0$ 1% 0& 1' 0( 0) #2211 0' #2296 b0 # 1$ #2302 0$ #2303 The code above defines 7 signals by using $var: $var type bitwidth id name The id is used later on the value change dump. The value change dump starts after $enddefinitions $end and is based on timestamps. Timestamp is denoted as '#' followed by number. On each timestamp the list of signals that change their value is listed. This is done by the value/id pair: new_value id This example will be displayed as Screenshot of GTKWave showing an example VCD file

External links

IEEE Std 1364-2001
– The official standard for Verilog 2001 (not free).
Compare VCD
– A command-line tool to compare VCD files (licensed under the GPL).
Verilog::VCD
– Perl CPAN software for parsing Verilog VCD files (licensed under the GPL).
Verilog_VCD
– Translated into Python from Perl CPAN software
ProcessVCD
– Java package for parsing VCD files (licensed under the MIT License).
PyVCD
– Python package that writes Value Change Dump (VCD) files as specified in IEEE 1364-2005 (MIT License).
Value Change Dump
– Explanation of VCD format, with example.
vcdMaker
– Tool (Linux, Windows) for translating text log files into VCD files (MIT License).
yne/vcd
– (Linux, Mac, Windows) CLI to Display VCD files on the terminal (MIT License). {{IEEE standards IEEE standards EDA file formats