Static timing analysis (STA) is a simulation method of computing the expected timing of a
synchronous digital circuit without requiring a simulation of the full circuit.
High-performance
integrated circuits have traditionally been characterized by the
clock frequency
In computing, the clock rate or clock speed typically refers to the frequency at which the clock generator of a processor can generate pulses, which are used to synchronize the operations of its components, and is used as an indicator of the pr ...
at which they operate. Measuring the ability of a circuit to operate at the specified speed requires an ability to measure, during the design process, its delay at numerous steps. Moreover,
delay calculation
Delay calculation is the term used in integrated circuit design for the calculation of the gate delay of a single logic gate and the wires attached to it. By contrast, static timing analysis computes the delays of entire paths, using delay calc ...
must be incorporated into the inner loop of timing optimizers at various phases of design, such as
logic synthesis
In computer engineering, logic synthesis is a process by which an abstract specification of desired circuit behavior, typically at register transfer level (RTL), is turned into a design implementation in terms of logic gates, typically by a com ...
, layout (
placement and
routing), and in in-place optimizations performed late in the design cycle. While such timing measurements can theoretically be performed using a rigorous
circuit simulation Electronic circuit simulation uses mathematical models to replicate the behavior of an actual electronic device or circuit.
Simulation software allows for modeling of circuit operation and is an invaluable analysis tool. Due to its highly accurat ...
, such an approach is liable to be too slow to be practical. Static timing analysis plays a vital role in facilitating the fast and reasonably accurate measurement of circuit timing. The speedup comes from the use of simplified timing models and by mostly ignoring logical interactions in circuits. This has become a mainstay of design over the last few decades.
One of the earliest descriptions of a static timing approach was based on the
Program Evaluation and Review Technique
The program evaluation and review technique (PERT) is a statistical tool used in project management, which was designed to analyze and represent the tasks involved in completing a given project.
First developed by the United States Navy in ...
(PERT), in 1966. More modern versions and algorithms appeared in the early 1980s.
Purpose
In a
synchronous digital system, data is supposed to move in
lockstep, advancing one stage on each tick of the
clock signal. This is enforced by synchronizing elements such as
flip-flops
Flip-flops are a type of light sandal, typically worn as a form of casual footwear. They consist of a flat sole held loosely on the foot by a Y-shaped strap known as a toe thong that passes between the first and second toes and around both side ...
or
latches, which copy their input to their output when instructed to do so by the clock. Only two kinds of timing errors are possible in such a system:
*A Max time violation, when a signal arrives too late, and misses the time when it should advance. These are more commonly known as setup violations/checks which actually are a subset of max time violations involving a cycle shift on synchronous paths.
*A Min time violation, when an input signal changes too soon after the clock's active transition. These are more commonly known as hold violations/checks which actually are a subset of min time violations in synchronous path.
The time when a signal arrives can vary due to many reasons. The input data may vary, the circuit may perform different operations, the temperature and voltage may change, and there are manufacturing differences in the exact construction of each part. The main goal of static timing analysis is to verify that despite these possible variations, all signals will arrive neither too early nor too late, and hence proper circuit operation can be assured.
Since STA is capable of verifying every path, it can detect other problems like
glitches
A glitch is a short-lived fault in a system, such as a transient fault that corrects itself, making it difficult to troubleshoot. The term is particularly common in the computing and electronics industries, in circuit bending, as well as amo ...
, slow paths and
clock skew Clock skew (sometimes called timing skew) is a phenomenon in synchronous digital circuit systems (such as computer systems) in which the same sourced clock signal arrives at different components at different times due to gate or, in more advanced ...
.
Definitions
* The critical path is defined as the path between an input and an output with the maximum delay. Once the circuit timing has been computed by one of the techniques listed below, the critical path can easily be found by using a traceback method.
* The arrival time of a signal is the time elapsed for a signal to arrive at a certain point. The reference, or time 0.0, is often taken as the
arrival time Time of arrival (TOA or ToA) is the absolute time instant when a radio signal emanating from a transmitter reaches a remote receiver.
The time span elapsed since the time of transmission (TOT or ToT) is the ''time of flight'' (TOF or ToF).
Time diff ...
of a clock signal. To calculate the arrival time,
delay calculation
Delay calculation is the term used in integrated circuit design for the calculation of the gate delay of a single logic gate and the wires attached to it. By contrast, static timing analysis computes the delays of entire paths, using delay calc ...
of all the components in the path will be required. Arrival times, and indeed almost all times in timing analysis, are normally kept as a pair of values - the earliest possible time at which a signal can change, and the latest.
* Another useful concept is required time. This is the latest time at which a signal can arrive without making the clock cycle longer than desired. The computation of the required time proceeds as follows: at each primary output, the required times for rise/fall are set according to the specifications provided to the circuit. Next, a backward topological traversal is carried out, processing each gate when the required times at all of its fanouts are known.
* The slack associated with each connection is the difference between the required time and the arrival time. A ''positive slack'' s at some node implies that the arrival time at that node may be increased by s, without affecting the overall delay of the circuit. Conversely, ''negative slack'' implies that a path is too slow, and the path must be sped up (or the reference signal delayed) if the whole circuit is to work at the desired speed.
Corners and STA
Quite often, designers will want to qualify their design across many conditions. Behavior of an electronic circuit is often dependent on various factors in its environment like temperature or local voltage variations. In such a case either STA needs to be performed for more than one such set of conditions, or STA must be prepared to work with a range of possible delays for each component, as opposed to a single value.
With proper techniques, the patterns of condition variations are characterized and their extremes are recorded. Each extreme condition can be termed as a
corner
Corner may refer to:
People
*Corner (surname)
* House of Cornaro, a noble Venetian family (''Corner'' in Venetian dialect)
Places
*Corner, Alabama, a community in the United States
*Corner Inlet, Victoria, Australia
*Corner River, a tributary of ...
. Extremes in cell characteristics can be considered as ‘process, voltage and temperature (PVT) corners’ and extremes in net characteristics can be considered as ‘extraction corners’. Then each combination pattern of PVT extraction corners is referred to as a ‘timing corner’ as it represents a point where timing will be extreme. If the design works at each extreme condition, then under the assumption of
monotonic
In mathematics, a monotonic function (or monotone function) is a function between ordered sets that preserves or reverses the given order. This concept first arose in calculus, and was later generalized to the more abstract setting of ord ...
behavior, the design is also qualified for all intermediate points.
The use of corners in static timing analysis has several limitations. It may be overly optimistic, since it assumes perfect tracking: if one gate is fast, all gates are assumed fast, or if the voltage is low for one gate, it is also low for all others. Corners may also be overly pessimistic, for the worst case corner may seldom occur. In an IC, for example, it may not be rare to have one metal layer at the thin or thick end of its allowed range, but it would be very rare for all 10 layers to be at the same limit, since they are manufactured independently. Statistical STA, which replaces delays with distributions, and tracking with correlation, offers a more sophisticated approach to the same problem.
The most prominent techniques for STA
In static timing analysis, the word ''static'' alludes to the fact that this timing analysis is carried out in an input-independent manner, and purports to find the worst-case delay of the circuit over all possible input combinations. The computational efficiency (linear in the number of edges in the graph) of such an approach has resulted in its widespread use, even though it has some limitations. A method that is commonly referred to as
PERT
Pert or PERT may refer to:
Ships
* - see List of United States Navy ships: P
* , a World War II corvette, originally HMS ''Nepeta''
* ''Pert'' (sidewheeler), a 19th-century steamboat that operated in British Columbia, Canada
Statistics
* PE ...
is popularly used in STA. However, PERT is a misnomer, and the so-called PERT method discussed in most of the literature on timing analysis refers to the
critical path method (CPM) that is widely used in project management. While the CPM-based methods are the dominant ones in use today, other methods for traversing circuit graphs, such as
depth-first search, have been used by various timing analyzers.
Interface timing analysis
Many of the common problems in chip designing are related to interface timing between different components of the design. These can arise because of many factors including incomplete simulation models, lack of test cases to properly verify interface timing, requirements for synchronization, incorrect interface specifications, and lack of designer understanding of a component supplied as a 'black box'. There are specialized CAD tools designed explicitly to analyze interface timing, just as there are specific CAD tools to verify that an implementation of an interface conforms to the functional specification (using techniques such as
model checking).
Statistical static timing analysis (SSTA)
Statistical static timing analysis (SSTA) is a procedure that is becoming increasingly necessary to handle the complexities of process and environmental variations in integrated circuits.
See also
*
Dynamic timing verification Dynamic timing verification refers to verifying that an ASIC design is fast enough to run without errors at the targeted clock rate. This is accomplished by simulating the design files used to synthesize the integrated circuit
An integrated ...
*
Electronic design automation
*
Integrated circuit design
Integrated circuit design, or IC design, is a sub-field of electronics engineering, encompassing the particular logic and circuit design techniques required to design integrated circuits, or ICs. ICs consist of miniaturized electronic compon ...
*
Logic analyzer
A logic analyzer is an electronic instrument that captures and displays multiple signals from a digital system or digital circuit. A logic analyzer may convert the captured data into timing diagrams, protocol decodes, state machine traces, a ...
—for verification of STA
*
Logic simulation
Logic simulation is the use of simulation software to predict the behavior of digital circuits and hardware description languages. Simulation can be performed at varying degrees of physical abstraction, such as at the transistor level, gate le ...
*
Simulation
A simulation is the imitation of the operation of a real-world process or system over time. Simulations require the use of models; the model represents the key characteristics or behaviors of the selected system or process, whereas the s ...
*
Timing margin
Timing margin is an electronics term that defines the difference between the actual change in a signal and the latest time at which the signal can change in order for an electronic circuit to function correctly. It is used in the design of digit ...
*
Worst-case execution time The worst-case execution time (WCET) of a computational task is the maximum length of time the task could take to execute on a specific hardware platform.
What it is used for
Worst case execution time is typically used in reliable real-time sys ...
*
Signoff (electronic design automation)
In the automated design of integrated circuits, signoff (also written as sign-off) checks is the collective name given to a series of verification steps that the design must pass before it can be taped out. This implies an iterative process involv ...
Notes
References
*''Electronic Design Automation For Integrated Circuits Handbook'', by Lavagno, Martin, and Scheffer, A survey of the field. This article was derived from Volume II, Chapter 8, 'Static Timing Analysis' by Sachin Sapatnekar, with permission.
*''Static Timing Analysis for Nanometer Designs'', by R. Chadha and J. Bhasker, {{ISBN, 978-0-387-93819-6, Springer, 2009.
Timing in electronic circuits
Formal methods