Features
Workspaces
On the TI-990, registers are stored in memory and are referred to through a hard register called the Workspace Pointer. The concept behind the workspace is that main memory was based on the new semiconductor RAM chips that TI had developed and ran at the same speed as the CPU. This meant that it didn't matter if the "registers" were real registers in the CPU or represented in memory. When the Workspace Pointer is loaded with a memory address, that address is the origin of the "registers." There are three hard registers in the 990; the Workspace Pointer (WP), the Program Counter (PC) and the Status register (ST). A context switch entailed the saving and restoring of only the hard registers.Extended operation
The TI-990 had a facility to allow extended operations through the use of plug in hardware. If the hardware is not present the CPU traps to allow software to perform the function. The operation code (XOP) allowed for 15 attached devices on a system. Although, device 15 is reserved, by convention, to be used as the systems call entry for user programs to request systems services.Orthogonal instruction set
The TI-990 used a fairlyArchitectural details
General register
TI-990 instructions
The 990/4, 990/5, 990/9 instruction sets consisted of 69 instructions, the 990/10 had 72 instructions, the 990/10A had 77 instructions and the 990/12 had 144 instructions. The instructions are divided into types that have similar characteristics.Assembly Language Programming Example
A complete " Hello, world!" program in TI-990 assembler, to run under DX10: IDT 'HELLO' TITL 'HELLO - hello world program' * DXOP SVC,15 Define SVC TMLUNO EQU 0 Terminal LUNO * R0 EQU 0 R1 EQU 1 R2 EQU 2 R3 EQU 3 R4 EQU 4 R5 EQU 5 R6 EQU 6 R7 EQU 7 R8 EQU 8 R9 EQU 9 R10 EQU 10 R11 EQU 11 R12 EQU 12 R13 EQU 13 R14 EQU 14 R15 EQU 15 * DATA WP,ENTRY,0 * * Workspace (On the 990 we can "preload" registers) * WP DATA 0 R0 DATA 0 R1 DATA >1600 R2 - End of program SVC DATA >0000 R3 - Open I/O opcode DATA >0B00 R4 - Write I/O opcode DATA >0100 R5 - Close I/O opcode DATA STRING R6 - Message address DATA STRLEN R7 - Message length DATA 0 R8 DATA 0 R9 DATA 0 R10 DATA 0 R11 DATA 0 R12 DATA 0 R13 DATA 0 R14 DATA 0 R15 * * Terminal SVC block * TRMSCB BYTE 0 SVC op code (0 = I/O) TRMERR BYTE 0 Error code TRMOPC BYTE 0 I/O OP CODE TRMLUN BYTE TMLUNO LUNO TRMFLG DATA 0 Flags TRMBUF DATA $-$ Buffer address TRMLRL DATA $-$ Logical record length TRMCHC DATA $-$ Character count * * Message * STRING TEXT 'Hello world!' BYTE >D,>A STRLEN EQU $-STRING EVEN PAGE * * Main program entry * ENTRY MOVB R3,@TRMOPC Set open opcode in SCB SVC @TRMSCB Open terminal MOVB @TRMERR,R0 Check for error JNE EXIT MOVB R4,@TRMOPC Set write opcode MOV R6,@TRMBUF Set buffer address MOV R7,@TRMLRL Set logical record length MOV R7,@TRMCHC and character count SVC @TRMSCB Write message MOVB @TRMERR,R0 Check for error JNE CLOSE CLOSE MOVB R5,@TRMOPC Set close opcode SVC @TRMSCB Close terminal EXIT SVC R2 Exit program * END You can try out the above for yourself on a TI-990 simulator. Dave Pitts's sim990 simulates the TI-990 and includes software kits for native operating systems (including DX10). The following program is a standalone version that prints on the serial terminal connected to CRU address 0. It illustrates the CRU I/O and workspace linkage for the PRINT subroutine. IDT 'HELLO' TITL 'HELLO - hello world program' * R0 EQU 0 R1 EQU 1 R2 EQU 2 R3 EQU 3 R4 EQU 4 R5 EQU 5 R6 EQU 6 R7 EQU 7 R8 EQU 8 R9 EQU 9 R10 EQU 10 R11 EQU 11 R12 EQU 12 R13 EQU 13 R14 EQU 14 R15 EQU 15 * * Terminal CRU bits * TRMCRU EQU >0 Terminal device address XMIT EQU 8 DTR EQU 9 RTS EQU 10 WRQ EQU 11 RRQ EQU 12 NSF EQU 13 * PAGE * * Main program entry * ENTRY LWPI WP Load our workspace pointer BLWP @PRINT Call our print routine DATA STRING DATA STRLEN IDLE * WP BSS 32 Main program workspace * * Message * STRING TEXT 'Hello world!' BYTE >D,>A STRLEN EQU $-STRING EVEN PAGE * * Print a message * PRINT DATA PRWS,PRENT PRENT EQU $ MOV *R14+,R2 Get buffer address MOV *R14+,R1 Get message length SBO DTR Enable terminal ready SBO RTS PRI010 LDCR *R2+,8 Send out a character TB WRQ Wait until done JNE $-2 SBZ WRQ DEC R1 JGT PRI010 RTWP * PRWS DATA 0,0,0,0,0,0,0,0 DATA 0,0,0,0,TRMCRU,0,0,0 * END ENTRYTI-990 models
The TI-990 processors fell into several natural groups depending on the original design upon which they are based and which I/O bus they used. All models supported the Communications Register Unit (CRU) which is a serial bit addressable I/O bus. Also, supported on higher end models was the TILINE I/O bus which is similar to DEC's popularTILINE/CRU models
The following models used the TILINE as their principal mass storage bus: *TI-990/5 — TMS-9900 microprocessor with 64K bytes of memory *TI-990/10 — TTL processor with memory mapping support to 2M bytes ofCRU only models
The following models used the CRU as their principal bus: *TI-990/4 — TMS-9900 microprocessor with 56K bytes of memory *TI-990/9 — The original TTL implementationOperating systems
SeveralSources
External links