Semulation is a

computer science Computer science is the study of computation, information, and automation. Computer science spans Theoretical computer science, theoretical disciplines (such as algorithms, theory of computation, and information theory) to Applied science, ...

-related

portmanteau In linguistics, a blend—also known as a blend word, lexical blend, or portmanteau—is a word formed by combining the meanings, and parts of the sounds, of two or more words together.

simulation A simulation is an imitative representation of a process or system that could exist in the real world. In this broad sense, simulation can often be used interchangeably with model. Sometimes a clear distinction between the two terms is made, in ...

and emulation, signifying the process of controlling an emulation through a simulator.

Semulation in computer science

Digital hardware Digital electronics is a field of electronics involving the study of digital signals and the engineering of devices that use or produce them. It deals with the relationship between binary inputs and outputs by passing electrical signals through ...

is described using

hardware description language In computer engineering, a hardware description language (HDL) is a specialized computer language used to describe the structure and behavior of electronic circuits, usually to design application-specific integrated circuits (ASICs) and to progra ...

s (HDL) like

VHDL VHDL (Very High Speed Integrated Circuit Program, VHSIC Hardware Description Language) is a hardware description language that can model the behavior and structure of Digital electronics, digital systems at multiple levels of abstraction, ran ...

Verilog Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits, with the highest level of abstraction being at the re ...

System Verilog SystemVerilog, technical standard, standardized as IEEE 1800 by the Institute of Electrical and Electronics Engineers (IEEE), is a Hardware description language, hardware description and hardware verification language commonly used to model, Har ...

. These descriptions are simulated together with a problem-specific testbench. The initial

functional verification Functional verification is the task of verifying that the digital circuit, logic design conforms to specification. Functional verification attempts to answer the question "Does this proposed design do what is intended?" This is complex and takes ...

of most IP designs is done via simulation at register transfer level (RTL) or gate level. In an event driven simulation method the code must be processed sequential by a CPU, because a normal computer is not able to process the implemented hardware parallel. This sequential approach leads to long simulation times especially in complex systems on chip (SoC) designs. After simulation the RTL description must be synthesized to fit in the final hardware (e.g.

FPGA A field-programmable gate array (FPGA) is a type of configurable integrated circuit that can be repeatedly programmed after manufacturing. FPGAs are a subset of logic devices referred to as programmable logic devices (PLDs). They consist of a ...

ASIC An application-specific integrated circuit (ASIC ) is an integrated circuit (IC) chip customized for a particular use, rather than intended for general-purpose use, such as a chip designed to run in a digital voice recorder or a high-efficien ...

). This step brings a lot of uncertainties because the real hardware is normally not as ideal as the simulation model. The differences between real world and simulation are a major reason why emulation is used in hardware design. Generally the simulation and emulation environment are two independent systems. Semulation is a symbiosis of both methods. In semulation one part of a hardware design is processed sequential in software (e.g. the testbench) while the other part is emulated. An example design flow for semulation is depicted in the following block chart: The database holds the design and testbench files and the information about the block whether it will be simulated or emulated. The left part shows the normal simulation path where the design files must be compiled for an HDL simulator. The right part of the state chart handles the flow for the emulation system. Design files for the FPGA must be synthesized to the appropriate target technology. A major point in semulation is the connection between the emulation system and the HDL simulator. The interface is necessary for the simulator to handle the connected hardware.

Advantages of Semulation

* Simulation acceleration: Simulating huge designs with an HDL simulator is a tedious task. When the designer transfers parts of the design to an emulation system and co-simulates them with the HDL simulation, the simulation run times can be decreased. * Using real hardware early in the design flow.

References

* D. Scheurer and S. Reichör
SEmulation: Turbocharging the FPGA Development Process
White Paper, Altera Corporation

External links

SEmulation Technology Combines ReConfigurable Computing-based Simulation and Emulation into a Single Platform for RTL Design Verification

SDC to Showcase SEmulation for FPGA Development at Embedded Masterclass

Semulation in EETimes
Electronic circuit verification