SPARC (Scalable Processor Architecture) is a reduced instruction set computer (RISC) instruction set architecture originally developed by Sun Microsystems. Its design was strongly influenced by the experimental

Berkeley RISC Berkeley RISC is one of two seminal research projects into reduced instruction set computer (RISC) based microprocessor design taking place under the Defense Advanced Research Projects Agency '' Very Large Scale Integration'' (VLSI) VLSI Project. ...

system developed in the early 1980s. First developed in 1986 and released in 1987, SPARC was one of the most successful early commercial RISC systems, and its success led to the introduction of similar RISC designs from many vendors through the 1980s and 1990s. The first implementation of the original 32-bit architecture (SPARC V7) was used in Sun's

Sun-4 Sun-4 is a series of Unix workstations and servers produced by Sun Microsystems, launched in 1987. The original Sun-4 series were VMEbus-based systems similar to the earlier Sun-3 series, but employing microprocessors based on Sun's own SPARC V7 RIS ...

computer

workstation A workstation is a special computer designed for technical or scientific applications. Intended primarily to be used by a single user, they are commonly connected to a local area network and run multi-user operating systems. The term ''workstat ...

and

server Server may refer to: Computing *Server (computing), a computer program or a device that provides functionality for other programs or devices, called clients Role * Waiting staff, those who work at a restaurant or a bar attending customers and su ...

systems, replacing their earlier

Sun-3 Sun-3 is a series of UNIX computer workstations and servers produced by Sun Microsystems, launched on September 9, 1985. The Sun-3 series are VMEbus-based systems similar to some of the earlier Sun-2 series, but using the Motorola 68020 microp ...

systems based on the

Motorola 68000 series The Motorola 68000 series (also known as 680x0, m68000, m68k, or 68k) is a family of 32-bit complex instruction set computer (CISC) microprocessors. During the 1980s and early 1990s, they were popular in personal computers and workstations and ...

of processors. SPARC V8 added a number of improvements that were part of the

SuperSPARC The SuperSPARC is a microprocessor that implements the SPARC V8 instruction set architecture (ISA) developed by Sun Microsystems. 33 and 40 MHz versions were introduced in 1992. The SuperSPARC contains 3.1 million transistors. It was fabricat ...

series of processors released in 1992. SPARC V9, released in 1993, introduced a

64-bit In computer architecture, 64-bit integers, memory addresses, or other data units are those that are 64 bits wide. Also, 64-bit CPUs and ALUs are those that are based on processor registers, address buses, or data buses of that size. A compu ...

architecture and was first released in Sun's

UltraSPARC The UltraSPARC is a microprocessor developed by Sun Microsystems and fabricated by Texas Instruments, introduced in mid-1995. It is the first microprocessor from Sun to implement the 64-bit SPARC V9 instruction set architecture (ISA). Marc Tr ...

processors in 1995. Later, SPARC processors were used in symmetric multiprocessing (SMP) and

non-uniform memory access Non-uniform memory access (NUMA) is a computer memory design used in multiprocessing, where the memory access time depends on the memory location relative to the processor. Under NUMA, a processor can access its own local memory faster than non ...

(

CC-NUMA Non-uniform memory access (NUMA) is a computer memory design used in multiprocessing, where the memory access time depends on the memory location relative to the processor. Under NUMA, a processor can access its own local memory faster than non ...

) servers produced by Sun, Solbourne, and Fujitsu, among others. The design was turned over to the SPARC International trade group in 1989, and since then its architecture has been developed by its members. SPARC International is also responsible for licensing and promoting the SPARC architecture, managing SPARC trademarks (including SPARC, which it owns), and providing

conformance testing Conformance testing — an element of conformity assessment, and also known as compliance testing, or type testing — is testing or other activities that determine whether a process, product, or service complies with the requirements of a specifi ...

. SPARC International was intended to grow the SPARC architecture to create a larger ecosystem; SPARC has been licensed to several manufacturers, including Atmel,

Bipolar Integrated Technology Bipolar Integrated Technology was a semiconductor company based in Beaverton, Oregon which sold products implemented with ECL technology. The company was founded in 1983 by former Floating Point Systems, Intel, and Tektronix engineers. The ini ...

Cypress Semiconductor Cypress Semiconductor was an American semiconductor design and manufacturing company. It offered NOR flash memories, F-RAM and SRAM Traveo microcontrollers, PSoC programmable system-on-chip solutions, analog and PMIC Power Management ICs, Ca ...

, Fujitsu, Matsushita and

Texas Instruments Texas Instruments Incorporated (TI) is an American technology company headquartered in Dallas, Texas, that designs and manufactures semiconductors and various integrated circuits, which it sells to electronics designers and manufacturers globa ...

. Due to SPARC International, SPARC is fully open, non-proprietary and royalty-free. As of September 2017, the latest commercial high-end SPARC processors are Fujitsu's SPARC64 XII (introduced in 2017 for its SPARC M12 server) and Oracle's SPARC M8 introduced in September 2017 for its high-end servers. On Friday, September 1, 2017, after a round of layoffs that started in Oracle Labs in November 2016, Oracle terminated SPARC design after completing the M8. Much of the processor core development group in Austin, Texas, was dismissed, as were the teams in Santa Clara, California, and Burlington, Massachusetts. Fujitsu will also discontinue their SPARC production (has already shifted to producing their own ARM-based CPUs), after two "enhanced" versions of Fujitsu's older SPARC M12 server in 2020–22 (formerly planned for 2021) and again in 2026–27, end-of-sale in 2029, of UNIX servers and a year later for their mainframe and end-of-support in 2034 "to promote customer modernization".

Features

The SPARC architecture was heavily influenced by the earlier RISC designs, including the RISC I and II from the

University of California, Berkeley The University of California, Berkeley (UC Berkeley, Berkeley, Cal, or California) is a public land-grant research university in Berkeley, California. Established in 1868 as the University of California, it is the state's first land-grant u ...

and the

IBM 801 The 801 was an experimental central processing unit (CPU) design developed by IBM during the 1970s. It is considered to be the first modern RISC design, relying on processor registers for all computations and eliminating the many variant addressi ...

. These original RISC designs were minimalist, including as few features or op-codes as possible and aiming to execute instructions at a rate of almost one instruction per

clock cycle In electronics and especially synchronous digital circuits, a clock signal (historically also known as ''logic beat'') oscillates between a high and a low state and is used like a metronome to coordinate actions of digital circuits. A clock sig ...

. This made them similar to the

MIPS architecture MIPS (Microprocessor without Interlocked Pipelined Stages) is a family of reduced instruction set computer (RISC) instruction set architectures (ISA)Price, Charles (September 1995). ''MIPS IV Instruction Set'' (Revision 3.2), MIPS Technologies, ...

in many ways, including the lack of instructions such as multiply or divide. Another feature of SPARC influenced by this early RISC movement is the

branch delay slot In computer architecture, a delay slot is an instruction slot being executed without the effects of a preceding instruction. The most common form is a single arbitrary instruction located immediately after a branch instruction on a RISC or DSP ...

. The SPARC processor usually contains as many as 160

general-purpose registers A processor register is a quickly accessible location available to a computer's processor. Registers usually consist of a small amount of fast storage, although some registers have specific hardware functions, and may be read-only or write-only. ...

. According to the "Oracle SPARC Architecture 2015" specification an "implementation may contain from 72 to 640 general-purpose 64-bit" registers. At any point, only 32 of them are immediately visible to software — 8 are a set of global registers (one of which, g0, is hard-wired to zero, so only seven of them are usable as registers) and the other 24 are from the stack of registers. These 24 registers form what is called a

register window In computer engineering, register windows are a feature which dedicates registers to a subroutine by dynamically aliasing a subset of internal registers to fixed, programmer-visible registers. Register windows are implemented to improve the perf ...

, and at function call/return, this window is moved up and down the register stack. Each window has 8 local registers and shares 8 registers with each of the adjacent windows. The shared registers are used for passing function parameters and returning values, and the local registers are used for retaining local values across function calls. The "Scalable" in SPARC comes from the fact that the SPARC specification allows implementations to scale from embedded processors up through large server processors, all sharing the same core (non-privileged) instruction set. One of the architectural parameters that can scale is the number of implemented register windows; the specification allows from three to 32 windows to be implemented, so the implementation can choose to implement all 32 to provide maximum

call stack In computer science, a call stack is a stack data structure that stores information about the active subroutines of a computer program. This kind of stack is also known as an execution stack, program stack, control stack, run-time stack, or m ...

efficiency, or to implement only three to reduce cost and complexity of the design, or to implement some number between them. Other architectures that include similar register file features include

Intel i960 Intel's i960 (or 80960) was a RISC-based microprocessor design that became popular during the early 1990s as an embedded microcontroller. It became a best-selling CPU in that segment, along with the competing AMD 29000. In spite of its success, ...

IA-64 IA-64 (Intel Itanium architecture) is the instruction set architecture (ISA) of the Itanium family of 64-bit Intel microprocessors. The basic ISA specification originated at Hewlett-Packard (HP), and was subsequently implemented by Intel in col ...

, and

AMD 29000 The AMD Am29000, commonly shortened to 29k, is a family of 32-bit RISC microprocessors and microcontrollers developed and fabricated by Advanced Micro Devices (AMD). Based on the seminal Berkeley RISC, the 29k added a number of significant impr ...

. The architecture has gone through several revisions. It gained hardware multiply and divide functionality in Version 8.

(addressing and data) were added to the version 9 SPARC specification published in 1994. In SPARC Version 8, the floating-point register file has 16 double-precision registers. Each of them can be used as two

single-precision Single-precision floating-point format (sometimes called FP32 or float32) is a computer number format, usually occupying 32 bits in computer memory; it represents a wide dynamic range of numeric values by using a floating radix point. A floatin ...

registers, providing a total of 32 single-precision registers. An odd-even number pair of double-precision registers can be used as a quad-precision register, thus allowing 8 quad-precision registers. SPARC Version 9 added 16 more double-precision registers (which can also be accessed as 8 quad-precision registers), but these additional registers can not be accessed as single-precision registers. No SPARC CPU implements quad-precision operations in hardware as of 2004.

Tagged Tagged may refer to: * Tagged (website), a social discovery website * Tagged (web series), an American teen psychological thriller web series {{disambiguation ...

add and subtract instructions perform adds and subtracts on values checking that the bottom two bits of both operands are 0 and reporting overflow if they are not. This can be useful in the implementation of the

run time Run(s) or RUN may refer to: Places * Run (island), one of the Banda Islands in Indonesia * Run (stream), a stream in the Dutch province of North Brabant People * Run (rapper), Joseph Simmons, now known as "Reverend Run", from the hip-hop group ...

for ML, Lisp, and similar languages that might use a tagged integer format. The

endianness In computing, endianness, also known as byte sex, is the order or sequence of bytes of a word of digital data in computer memory. Endianness is primarily expressed as big-endian (BE) or little-endian (LE). A big-endian system stores the mos ...

of the 32-bit SPARC V8 architecture is purely big-endian. The 64-bit SPARC V9 architecture uses big-endian instructions, but can access data in either big-endian or little-endian byte order, chosen either at the application instruction ( load–store) level or at the

memory page A page, memory page, or virtual page is a fixed-length contiguous block of virtual memory, described by a single entry in the page table. It is the smallest unit of data for memory management in a virtual memory operating system. Similarly, a p ...

level (via an MMU setting). The latter is often used for accessing data from inherently little-endian devices, such as those on PCI buses.

History

There have been three major revisions of the architecture. The first published version was the 32-bit ''SPARC Version 7'' (V7) in 1986. ''SPARC Version 8'' (V8), an enhanced SPARC architecture definition, was released in 1990. The main differences between V7 and V8 were the addition of integer multiply and divide instructions, and an upgrade from 80-bit "extended-precision" floating-point arithmetic to 128-bit " quad-precision" arithmetic. SPARC V8 served as the basis for IEEE Standard 1754-1994, an

IEEE The Institute of Electrical and Electronics Engineers (IEEE) is a 501(c)(3) professional association for electronic engineering and electrical engineering (and associated disciplines) with its corporate office in New York City and its operat ...

standard for a 32-bit microprocessor architecture. ''SPARC Version 9'', the 64-bit SPARC architecture, was released by SPARC International in 1993. It was developed by the SPARC Architecture Committee consisting of

Amdahl Corporation Amdahl Corporation was an information technology company which specialized in IBM mainframe-compatible computer products, some of which were regarded as supercomputers competing with those from Cray Research. Founded in 1970 by Gene Amdahl, a for ...

, Fujitsu, ICL,

LSI Logic LSI Logic Corporation, an American company founded in Milpitas, California, was a pioneer in the ASIC and EDA industries. It evolved over time to design and sell semiconductors and software that accelerated storage and networking in data center ...

, Matsushita,

Philips Koninklijke Philips N.V. (), commonly shortened to Philips, is a Dutch multinational conglomerate corporation that was founded in Eindhoven in 1891. Since 1997, it has been mostly headquartered in Amsterdam, though the Benelux headquarters i ...

Ross Technology Ross Technology, Inc. was a semiconductor design and manufacturing company, specializing in SPARC microprocessors. It was founded in Austin, Texas in August 1988 by Dr. Roger D. Ross, a leading computer scientist who headed Motorola's Advanced ...

, Sun Microsystems, and

. Newer specifications always remain compliant with the full SPARC V9 Level 1 specification. In 2002, the SPARC ''Joint Programming Specification 1'' (JPS1) was released by Fujitsu and Sun, describing processor functions which were identically implemented in the CPUs of both companies ("Commonality"). The first CPUs conforming to JPS1 were the UltraSPARC III by Sun and the SPARC64 V by Fujitsu. Functionalities which are not covered by JPS1 are documented for each processor in "Implementation Supplements". At the end of 2003, JPS2 was released to support multicore CPUs. The first CPUs conforming to JPS2 were the UltraSPARC IV by Sun and the SPARC64 VI by Fujitsu. In early 2006, Sun released an extended architecture specification, ''UltraSPARC Architecture 2005''. This includes not only the non-privileged and most of the privileged portions of SPARC V9, but also all the architectural extensions developed through the processor generations of UltraSPARC III, IV IV+ as well as CMT extensions starting with the

UltraSPARC T1 Sun Microsystems' UltraSPARC T1 microprocessor, known until its 14 November 2005 announcement by its development codename "Niagara", is a multithreading, multicore CPU. Designed to lower the energy consumption of server computers, the CPU typ ...

implementation: * the VIS 1 and VIS 2 instruction set extensions and the associated GSR register * multiple levels of global registers, controlled by the GL register * Sun's 64-bit MMU architecture * privileged instructions ALLCLEAN, OTHERW, NORMALW, and INVALW * access to the VER register is now hyperprivileged * the SIR instruction is now hyperprivileged In 2007, Sun released an updated specification, ''UltraSPARC Architecture 2007'', to which the

UltraSPARC T2 Sun Microsystems' UltraSPARC T2 microprocessor is a multithreading, multi-core CPU. It is a member of the SPARC family, and the successor to the UltraSPARC T1. The chip is sometimes referred to by its codename, Niagara 2. Sun started selling ...

implementation complied. In August 2012, Oracle Corporation made available a new specification, ''Oracle SPARC Architecture 2011'', which besides the overall update of the reference, adds the VIS 3 instruction set extensions and hyperprivileged mode to the 2007 specification. In October 2015, Oracle released SPARC M7, the first processor based on the new ''Oracle SPARC Architecture 2015'' specification. This revision includes VIS 4 instruction set extensions and hardware-assisted encryption and silicon secured memory (SSM). SPARC architecture has provided continuous application binary compatibility from the first SPARC V7 implementation in 1987 through the Sun UltraSPARC Architecture implementations. Among various implementations of SPARC, Sun's SuperSPARC and UltraSPARC-I were very popular, and were used as reference systems for

SPEC Spec may refer to: *Specification (technical standard), an explicit set of requirements to be satisfied by a material, product, or service **datasheet, or "spec sheet" People * Spec Harkness (1887-1952), American professional baseball pitcher ...

CPU95 and CPU2000 benchmarks. The 296 MHz UltraSPARC-II is the reference system for the SPEC CPU2006 benchmark.

Architecture

SPARC is a load/store architecture (also known as a ''register-register architecture''); except for the load/store instructions used to access

memory Memory is the faculty of the mind by which data or information is encoded, stored, and retrieved when needed. It is the retention of information over time for the purpose of influencing future action. If past events could not be remembered ...

, all instructions operate on the registers, in accordance with the RISC design principles.

Registers

The SPARC architecture has an overlapping register window scheme. At any instant, 32 general purpose registers are visible. A Current Window Pointer (''CWP'') variable in the hardware points to the current set. The total size of the register file is not part of the architecture, allowing more registers to be added as the technology improves, up to a maximum of 32 windows in SPARC V7 and V8 as ''CWP'' is 5 bits and is part of the ''PSR'' register. In SPARC V7 and V8 ''CWP'' will usually be decremented by the SAVE instruction (used by the SAVE instruction during the procedure call to open a new stack frame and switch the register window), or incremented by the RESTORE instruction (switching back to the call before returning from the procedure). Trap events (interrupts, exceptions or TRAP instructions) and RETT instructions (returning from traps) also change the ''CWP''. For SPARC V9, CWP register is decremented during a RESTORE instruction, and incremented during a SAVE instruction. This is the opposite of PSR.CWP's behavior in SPARC V8. This change has no effect on nonprivileged instructions. SPARC registers are shown in the figure above.

Instruction formats

All SPARC instructions occupy a full 32 bit word and start on a word boundary. Four formats are used, distinguished by the first two bits. All arithmetic and logical instructions have 2 source operands and 1 destination operand. SETHI instruction format copies its 22 bit immediate operand into the high-order 22 bits of any specified register, and sets each of the low-order 10 bits to 0. Format ALU register, both sources are registers; format ALU immediate, one source is a register and one is a constant in the range -4096 to +4095. Bit 13 selects between them. In both cases, the destination is always a register. Branch format instructions do control transfers or conditional branches. The icc or fcc field specifies the kind of branch. The 22 bit displacement field give the relative address of the target in words so that conditional branches can go forward or backward up to 8 megabytes. The ''ANNUL'' (A) bit is used to get rid of some delay slots. If it is 0 in a conditional branch, the delay slot is executed as usual. If it is 1, the delay slot is only executed if the branch is taken. If it is not taken, the instruction following the conditional branch is skipped. The CALL instruction uses a 30-bit program counter-relative word offset. This value is enough to reach any instruction within 4 gigabytes of the caller or the entire address space. The CALL instruction deposits the return address in register R15 also known as output register O7. Just like the arithmetic instructions, the SPARC architecture uses two different formats for load and store instructions. The first format is used for instructions that use one or two registers as the effective address. The second format is used for instructions that use an integer constant as the effective address. Most arithmetic instructions come in pairs with one version setting the NZVC condition code bits, and the other does not. This is so that the compiler has a way to move instructions around when trying to fill delay slots. SPARC V7 does not have multiplication or division instructions, but it does have MULSCC, which does one step of a multiplication testing one bit and conditionally adding the multiplicand to the product. This was because MULSCC can complete over one clock cycle in keeping with the RISC philosophy.

SPARC architecture licensees

The following organizations have licensed the SPARC architecture: * Afara Websystems *

(BIT) *

* European Space Research and Technology Center (ESTEC) * Fujitsu (and its Fujitsu Microelectronics subsidiary) *

Gaisler Research Aeroflex Inc. was an American company which produced test equipment, RF and microwave integrated Integrated circuit, circuits, components and systems used for wireless communications. Its headquarters were located in Plainview, New York, Plainvie ...

HAL Computer Systems HAL Computer Systems, Inc was a Campbell, California-based computer manufacturer founded in 1990 by Andrew Heller, a principal designer of the original IBM POWER architecture. His idea was to build computers based on a RISC architecture for the ...

Hyundai Hyundai is a South Korean industrial conglomerate ("chaebol"), which was restructured into the following groups: * Hyundai Group, parts of the former conglomerate which have not been divested ** Hyundai Mobis, Korean car parts company ** Hyundai ...

* Matra Harris Semiconductors (MHS) * Matsushita Electrical Industrial Co. *

Meiko Scientific Meiko Scientific Ltd. was a British supercomputer company based in Bristol, founded by members of the design team working on the Inmos transputer microprocessor. History In 1985, when Inmos management suggested the release of the transputer b ...

* Metaflow Technologies *

Philips Electronics Koninklijke Philips N.V. (), commonly shortened to Philips, is a Dutch multinational conglomerate corporation that was founded in Eindhoven in 1891. Since 1997, it has been mostly headquartered in Amsterdam, though the Benelux headquarters i ...

* Prisma *

Solbourne Computer Solbourne Computer Inc. was originally a vendor of computer systems based in Longmont, Colorado, United States, at first 52% owned by Matsushita. In the late 1980s and early 1990s, the company produced a range of computer workstations and server ...

* Systems & Processes Engineering Corporation (SPEC) * TEMIC *

Weitek Weitek Corporation was an American chip-design company that originally focused on floating-point units for a number of commercial CPU designs. During the early to mid-1980s, Weitek designs could be found powering a number of high-end designs ...

Implementations

Notes:

Operating system support

SPARC machines have generally used Sun's SunOS, Solaris, or OpenSolaris including derivatives

illumos Illumos (stylized as illumos) is a partly free and open-source Unix operating system. It is based on OpenSolaris, which was based on System V Release 4 (SVR4) and the Berkeley Software Distribution (BSD). Illumos comprises a kernel, device d ...

and

OpenIndiana OpenIndiana is a free and open-source illumos distribution Unix-derived System V SVR4 operating system, started as OpenSolaris continuation project. Forked from OpenSolaris after OpenSolaris was discontinued by Oracle Corporation, OpenIndiana ...

, but other

operating system An operating system (OS) is system software that manages computer hardware, software resources, and provides common services for computer programs. Time-sharing operating systems schedule tasks for efficient use of the system and may also i ...

s have also been used, such as

NeXTSTEP NeXTSTEP is a discontinued object-oriented, multitasking operating system based on the Mach kernel and the UNIX-derived BSD. It was developed by NeXT Computer in the late 1980s and early 1990s and was initially used for its range of propri ...

RTEMS Real-Time Executive for Multiprocessor Systems (RTEMS), formerly Real-Time Executive for Missile Systems, and then Real-Time Executive for Military Systems, is a real-time operating system (RTOS) designed for embedded systems. It is free and open ...

, FreeBSD, OpenBSD, NetBSD, and

Linux Linux ( or ) is a family of open-source Unix-like operating systems based on the Linux kernel, an operating system kernel first released on September 17, 1991, by Linus Torvalds. Linux is typically packaged as a Linux distribution, w ...

. In 1993,

Intergraph Intergraph Corporation was an American software development and services company, which now forms part of Hexagon AB. It provides enterprise engineering and geospatially powered software to businesses, governments, and organizations around the w ...

announced a port of

Windows NT Windows NT is a proprietary graphical operating system produced by Microsoft, the first version of which was released on July 27, 1993. It is a processor-independent, multiprocessing and multi-user operating system. The first version of Win ...

to the SPARC architecture, but it was later cancelled. In October 2015, Oracle announced a "Linux for SPARC reference platform".

Open source implementations

Several fully open source implementations of the SPARC architecture exist: *

LEON Leon, Léon (French) or León (Spanish) may refer to: Places Europe * León, Spain, capital city of the Province of León * Province of León, Spain * Kingdom of León, an independent state in the Iberian Peninsula from 910 to 1230 and again f ...

, a 32-bit radiation-tolerant, SPARC V8 implementation, designed especially for space use.

Source code In computing, source code, or simply code, is any collection of code, with or without comments, written using a human-readable programming language, usually as plain text. The source code of a program is specially designed to facilitate the w ...

is written in

VHDL The VHSIC Hardware Description Language (VHDL) is a hardware description language (HDL) that can model the behavior and structure of digital systems at multiple levels of abstraction, ranging from the system level down to that of logic gate ...

, and licensed under the

GPL The GNU General Public License (GNU GPL or simply GPL) is a series of widely used free software licenses that guarantee end users the four freedoms to run, study, share, and modify the software. The license was the first copyleft for general u ...

. *

OpenSPARC OpenSPARC is an open-source hardware project started in December 2005. The initial contribution to the project was Sun Microsystems' register-transfer level (RTL) Verilog code for a full 64-bit, 32- thread microprocessor, the UltraSPARC T1 process ...

T1, released in 2006, a 64-bit, 32-thread implementation conforming to the UltraSPARC Architecture 2005 and to SPARC Version 9 (Level 1). Source code is written in

Verilog Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction. It is als ...

, and licensed under many licenses. Most OpenSPARC T1 source code is licensed under the GPL. Source based on existent open source projects will continue to be licensed under their current licenses. Binary programs are licensed under a binary

software license agreement An end-user license agreement or EULA () is a legal contract between a software supplier and a customer or end-user, generally made available to the customer via a retailer acting as an intermediary. A EULA specifies in detail the rights and restr ...

. * S1, a 64-bit Wishbone compliant CPU core based on the OpenSPARC T1 design. It is a single UltraSPARC V9 core capable of 4-way SMT. Like the T1, the source code is licensed under the GPL. *

T2, released in 2008, a 64-bit, 64-thread implementation conforming to the UltraSPARC Architecture 2007 and to SPARC Version 9 (Level 1). Source code is written in Verilog, and licensed under many licenses. Most OpenSPARC T2 source code is licensed under the GPL. Source based on existing open source projects will continue to be licensed under their current licenses. Binary programs are licensed under a binary Software License Agreement. A fully open source simulator for the SPARC architecture also exists:
RAMP Gold
a 32-bit, 64-thread SPARC Version 8 implementation, designed for FPGA-based architecture simulation. RAMP Gold is written in ~36,000 lines of

SystemVerilog SystemVerilog, standardized as IEEE 1800, is a hardware description and hardware verification language used to model, design, simulate, test and implement electronic systems. SystemVerilog is based on Verilog and some extensions, and since ...

, and licensed under the BSD licenses.

Supercomputers

For HPC loads Fujitsu builds specialized SPARC64 fx processors with a new instruction extensions set, called HPC-ACE (High Performance Computing – Arithmetic Computational Extensions). Fujitsu's

K computer The K computer named for the Japanese word/numeral , meaning 10 quadrillion (1016)See Japanese numbers was a supercomputer manufactured by Fujitsu, installed at the Riken Advanced Institute for Computational Science campus in Kobe, Hyōgo Pref ...

ranked in the

TOP500 The TOP500 project ranks and details the 500 most powerful non- distributed computer systems in the world. The project was started in 1993 and publishes an updated list of the supercomputers twice a year. The first of these updates always coinci ...

June 2011 and November 2011 lists. It combines 88,128 SPARC64 VIIIfx CPUs, each with eight cores, for a total of 705,024 cores—almost twice as many as any other system in the

at that time. The K Computer was more powerful than the next five systems on the list combined, and had the highest performance-to-power ratio of any supercomputer system. It also ranked in the

Green500 The Green500 is a biannual ranking of supercomputers, from the TOP500 list of supercomputers, in terms of energy efficiency. The list measures performance per watt using the TOP500 measure of high performance LINPACK benchmarks at double-precisi ...

June 2011 list, with a score of 824.56 MFLOPS/W. In the November 2012 release of

, the K computer ranked , using by far the most power of the top three. It ranked on the corresponding

release. Newer HPC processors, IXfx and XIfx, were included in recent

PRIMEHPC FX10 The PRIMEHPC FX10 is a supercomputer designed and manufactured by Fujitsu. Announced on 7 November 2011 at the Supercomputing Conference, the PRIMEHPC FX10 is an improved and commercialized version of the K computer, which was the first supercompute ...

and FX100 supercomputers.

Tianhe-2 Tianhe-2 or TH-2 (, i.e. 'Milky Way 2') is a 33.86- petaflops supercomputer located in the National Supercomputer Center in Guangzhou, China. It was developed by a team of 1,300 scientists and engineers. It was the world's fastest supercomputer ...

(

as of November 2014) has a number of nodes with Galaxy FT-1500

-based processors developed in China. However, those processors did not contribute to the LINPACK score.