A single cycle processor is a processor that carries out one instruction in a single
clock cycle
In electronics and especially synchronous digital circuits, a clock signal (historically also known as ''logic beat'') oscillates between a high and a low state and is used like a metronome to coordinate actions of digital circuits.
A clock sig ...
.
See also
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Complex instruction set computer
A complex instruction set computer (CISC ) is a computer architecture in which single instructions can execute several low-level operations (such as a load from memory, an arithmetic operation, and a memory store) or are capable of multi-step o ...
, a processor executing one instruction in multiple clock cycles
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DLX, a very similar architecture designed by
John L. Hennessy
John Leroy Hennessy (born September 22, 1952) is an American computer scientist, academician and businessman who serves as Chairman of Alphabet Inc. Hennessy is one of the founders of MIPS Computer Systems Inc. as well as Atheros and served as t ...
(creator of MIPS) for teaching purposes
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MIPS architecture
MIPS (Microprocessor without Interlocked Pipelined Stages) is a family of reduced instruction set computer (RISC) instruction set architectures (ISA)Price, Charles (September 1995). ''MIPS IV Instruction Set'' (Revision 3.2), MIPS Technologies, ...
, MIPS-32 architecture
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MIPS-X
MIPS-X is a reduced instruction set computer (RISC) microprocessor and instruction set architecture (ISA) developed as a follow-on project to the Stanford MIPS, MIPS project at Stanford University by the same team that developed MIPS. The project, ...
, developed as a follow-on project to the MIPS architecture
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Reduced instruction set computer, a processor executing one instruction in minimal clock cycles
References
External links
Microprocessors
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